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Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era最新文献

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Interaction in language based system level design using an advanced compiler generator environment 基于交互语言的系统级设计使用高级编译器生成环境
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844536
I. Poulakis, G. Economakos, P. Tsanakas
{"title":"Interaction in language based system level design using an advanced compiler generator environment","authors":"I. Poulakis, G. Economakos, P. Tsanakas","doi":"10.1109/IWV.2000.844536","DOIUrl":"https://doi.org/10.1109/IWV.2000.844536","url":null,"abstract":"Computer-aided synthesis of digital circuits from behavioural level specifications offers an effective way to deal with the increasing complexity of digital hardware design. A high-level synthesis tool transforms an abstract algorithmic description into a detailed register transfer level implementation. Even though considerable research has taken place, regarding high-level synthesis, practical implementations are just emerging. This happens due to the fact that designers demand interaction at both the specification and implementation level. This paper describes an efficient implementation of an original idea, for the design of a grammar based interactive design environment, which allows designers to supplement high-level synthesis optimizations and set constraints among the operators in the textual algorithmic description to meet their implementation preferences. The suggested methodology raises the feasibility for high level design space exploration by enabling synthesis results to be directly modifiable by the user.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131888632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Instruction scheduling based on energy and performance constraints 基于能量和性能约束的指令调度
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844527
A. Parikh, M. Kandemir, N. Vijaykrishnan, M. J. Irwin
{"title":"Instruction scheduling based on energy and performance constraints","authors":"A. Parikh, M. Kandemir, N. Vijaykrishnan, M. J. Irwin","doi":"10.1109/IWV.2000.844527","DOIUrl":"https://doi.org/10.1109/IWV.2000.844527","url":null,"abstract":"Reducing energy consumption has become an important issue in designing hardware and software systems in recent years. Although low power hardware components are critical for reducing energy consumption, the switching activity, which is the main source of dynamic power dissipation in electronic systems, is largely determined by the software running on these systems. In this paper we present and evaluate several instruction scheduling algorithms that reorder a given sequence of instructions taking into account the energy considerations. We first compare a performance-oriented scheduling technique with three energy-oriented instruction scheduling algorithms from both performance (execution cycles of the resulting schedules) and energy consumption points of view. Then, we propose three scheduling algorithms that consider energy and performance at the same time. The results obtained show that these techniques are quite successful in reducing energy consumption and their performance is comparable to that of a pure performance-oriented scheduling.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125808355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Reducing the power consumption in FPGAs with keeping a high performance level 在保持高性能水平的同时降低fpga的功耗
Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era Pub Date : 2000-04-27 DOI: 10.1109/IWV.2000.844529
A.D. Garcia G., W. Burleson, J. Danger
{"title":"Reducing the power consumption in FPGAs with keeping a high performance level","authors":"A.D. Garcia G., W. Burleson, J. Danger","doi":"10.1109/IWV.2000.844529","DOIUrl":"https://doi.org/10.1109/IWV.2000.844529","url":null,"abstract":"Power consumption is becoming an important constraint in VLSI design because of the increase of wireless and portable battery powered applications. On the other hand, the use of Field Programmable Gate Arrays (FPGAs) has been increasing largely due to the ability to rapidly develop prototypes with reduced development times and costs. A well known technique for low power operation in VLSI using the lowest possible supply voltage coupled with an architectural optimization is used to save power even when it increases silicon area. This technique implemented in FPGAs can represent several advantages. Since D-type flip-flops (DFFs) are for free inside each logic cell, pipeline architectures match naturally in FPGAs. Finally, some commercial FPGAs can work using a low supply voltage with no dramatic performance degradation.","PeriodicalId":300014,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115092071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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