[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture最新文献_第3页

Dynamic processor allocation in hypercube computers 超立方体计算机中的动态处理器分配

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325110

Po-Jen Chuang, N. Tzeng

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引用次数: 26

The TLB slice-a low-cost high-speed address translation mechanism TLB片——一种低成本的高速地址转换机制

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325161

G. Taylor, Peter Davies, M. Farmwald

引用次数: 126

An investigation of static versus dynamic scheduling 静态与动态调度的研究

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325140

C. Love, H. Jordan

引用次数: 11

APRIL: a processor architecture for multiprocessing 用于多处理的处理器体系结构

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325119

A. Agarwal, B. Lim, D. Kranz, J. Kubiatowicz

引用次数: 447

Adaptive software cache management for distributed shared memory architectures 分布式共享内存架构的自适应软件缓存管理

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325124

J. Bennett, J. Carter, W. Zwaenepoel

引用次数: 191

Maximizing performance in a striped disk array 在条带阵列中实现性能最大化

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325158

Peter M. Chen, D. Patterson

引用次数: 240

The impact of synchronization and granularity on parallel systems 同步和粒度对并行系统的影响

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325150

D. Chen, H. Su, P. Yew

引用次数: 95

The performance impact of block sizes and fetch strategies 块大小和获取策略对性能的影响

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325135

S. Przybylski

{"title":"The performance impact of block sizes and fetch strategies","authors":"S. Przybylski","doi":"10.1145/325164.325135","DOIUrl":"https://doi.org/10.1145/325164.325135","url":null,"abstract":"The interactions between a cache's block size, fetch size, and fetch policy from the perspective of maximizing system-level performance are explored. It has been previously noted that, given a simple fetch strategy, the performance optimal block size is almost always four or eight words. If there is even a small cycle time penalty associated with either longer blocks or fetches, then the performance optimal size is noticeably reduced. In split cache organizations, where the fetch and block sizes of instruction and data caches are all independent design variables, instruction cache block size and fetch size should be the same. For the workload and write-back write policy used in this trace-driven simulation study, the instruction cache block size should be about a factor of 2 greater than the data cache fetch size, which in turn should be equal to or double the data cache block size. The simplest fetch strategy of fetching only on a miss and stalling the CPU until the fetch is complete works well. Complicated fetch strategies do not produce the performance improvements indicated by the accompanying reductions in miss ratios because of limited memory resources and a strong temporal clustering of cache misses. For the environments simulated, the most effective fetch strategy improved performance by between 1.7% and 4.5% over the simplest strategy described above.<<ETX>>","PeriodicalId":297046,"journal":{"name":"[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122916996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 108

Trace-driven simulations for a two-level cache design of open bus systems 开放总线系统两级缓存设计的轨迹驱动仿真

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325151

Hakon O. Bugge, E. Kristiansen, B. O. Bakka

引用次数: 34

Boosting beyond static scheduling in a superscalar processor 超标量处理器中超越静态调度的提升

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325160

Michael D. Smith, M. Lam, M. Horowitz

引用次数: 145