[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture最新文献

A study of I/O behavior of Perfect benchmarks on a multiprocessor 多处理器上完美基准的I/O行为研究

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325157

A. Reddy, P. Banerjee

引用次数: 44

The directory-based cache coherence protocol for the DASH multiprocessor DASH多处理器基于目录的缓存一致性协议

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325132

D. Lenoski, J. Laudon, K. Gharachorloo, Anoop Gupta, J. Hennessy

{"title":"The directory-based cache coherence protocol for the DASH multiprocessor","authors":"D. Lenoski, J. Laudon, K. Gharachorloo, Anoop Gupta, J. Hennessy","doi":"10.1145/325164.325132","DOIUrl":"https://doi.org/10.1145/325164.325132","url":null,"abstract":"DASH is a scalable shared-memory multiprocessor whose architecture consists of powerful processing nodes, each with a portion of the shared-memory, connected to a scalable interconnection network. A key feature of DASH is its distributed direction-based cache coherence protocol. Unlike traditional snoopy coherence protocols, the DASH protocol does not rely on broadcast; instead it uses point-to-point messages sent between the processors and memories to keep caches consistent. Furthermore, the DASH system does not contain any single serialization or control point. While these features provide the basis for scalability, they also force a reevaluation of many fundamental issues involved in the design of a protocol. These include the issues of correctness, performance, and protocol complexity. The design of the DASH coherence protocol is presented and discussed from the viewpoint of how it addresses the above issues. Also discussed is a strategy for verifying the correctness of the protocol. A brief comparison of the protocol with the IEEE Scalable Coherent Interface protocol is made.<<ETX>>","PeriodicalId":297046,"journal":{"name":"[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115896369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 736

An empirical evaluation of two memory-efficient directory methods 两种内存效率目录方法的经验评价

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325130

Brian W. O'Krafka, A. Richard Newton

{"title":"An empirical evaluation of two memory-efficient directory methods","authors":"Brian W. O'Krafka, A. Richard Newton","doi":"10.1145/325164.325130","DOIUrl":"https://doi.org/10.1145/325164.325130","url":null,"abstract":"The authors present an empirical evaluation of two memory-efficient directory methods for maintaining coherent caches in large shared-memory multiprocessors. Both directory methods are modifications of a scheme proposed by L.M. Censier and P. Feautrier (1978) that does not rely on a specific interconnection network and can be readily distributed across interleaved main memory. The schemes considered here overcome the large amount of memory required for tags in the original scheme in two different ways. In the first scheme each main memory block is sectored into sub-blocks for which the large tag overhead is shared. In the second scheme a limited number of large tags are stored in an associative cache and shared among a much larger number of main memory blocks. Simulations show that in terms of access time and network traffic both directory methods provide significant performance improvements over a memory system in which shared-writable data are not cached. The large block sizes required for the sectored scheme, however, promote sufficient false sharing for its performance to be markedly worse than when a tag cache is used.<<ETX>>","PeriodicalId":297046,"journal":{"name":"[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125034042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 135

Performance comparison of load/store and symmetric instruction set architectures 加载/存储和对称指令集体系结构的性能比较

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325137

D. Alpert, A. Averbuch, O. Danieli

引用次数: 6

Performance of an OLTP application on Symmetry multiprocessor system 对称多处理器系统上OLTP应用程序的性能

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325149

S. Thakkar, Mark Sweiger

引用次数: 75

Balance in architectural design 建筑设计中的平衡

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325156

Samuel Ho, L. Snyder

引用次数: 1

Performance measurement and trace driven simulation of parallel CAD and numeric applications on a hypercube multicomputer 在超立方体多计算机上并行CAD和数值应用程序的性能测量和跟踪驱动仿真

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325152

Jiun-Ming Hsu, P. Banerjee

引用次数: 63

Supporting systolic and memory communication in iWarp 支持收缩和内存通信在iWarp

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325116

S. Borkar, R. Cohn, G. Cox, T. Gross, H. T. Kung, M. Lam, M. Levine, B. Moore, W. Moore, C. Peterson, J. Susman, J. Sutton, J. Urbanski, J. Webb

{"title":"Supporting systolic and memory communication in iWarp","authors":"S. Borkar, R. Cohn, G. Cox, T. Gross, H. T. Kung, M. Lam, M. Levine, B. Moore, W. Moore, C. Peterson, J. Susman, J. Sutton, J. Urbanski, J. Webb","doi":"10.1145/325164.325116","DOIUrl":"https://doi.org/10.1145/325164.325116","url":null,"abstract":"The iWarp communication system supports two widely used interprocessor communication styles: memory communication and systolic communication. A description is given of the rationale, architecture, and implementation for the iWarp communication system. Memory communication is flexible and well suited for general computing, whereas systolic communication is efficient and well suited for speed-critical applications. The iWarp design is made possible by two important innovations in communication: (1) program access to communication and (2) logical channels. The former allows programs to access data as they are transmitted and to redirect portions of messages to different destinations efficiently. The latter increases the connectivity between the processors and guarantees communication bandwidth for classes of messages. These innovations have provided a focus for the iWarp architecture. The result is a communication system that provides a total bandwidth of 320 MBytes/sec and that is integrated on a single VLSI component with a 20 MFLOPS plus 20 MIPS long instruction work computation engine.<<ETX>>","PeriodicalId":297046,"journal":{"name":"[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 210

Virtual-channel flow control 虚拟通道流量控制

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/325164.325115

W. Dally

引用次数: 1658

Weak ordering-a new definition 弱有序——一个新的定义

[1990] Proceedings. The 17th Annual International Symposium on Computer Architecture Pub Date : 1990-05-01 DOI: 10.1145/285930.285996

S. Adve, M. Hill

引用次数: 178