APRIL: a processor architecture for multiprocessing

A. Agarwal, B. Lim, D. Kranz, J. Kubiatowicz
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引用次数: 447

Abstract

The architecture of a rapid-context-switching processor called APRIL, with support for fine-grain threads and synchronization, is described. APRIL achieves high single-thread performance and supports virtual dynamic threads. A commercial reduced-instruction-set-computer-(RISC-) based implementation of APRIL and a run-time software system that can switch contexts in about 10 cycles are described. Measurements taken for several parallel applications on an APRIL simulator show that the overhead for supporting parallel tasks based on futures is reduced by a factor of 2 over a corresponding implementation on the Encore Multimax. The scalability of a multiprocessor based on APRIL is explored using a performance model. The authors show that the SPARC-based implementation of APRIL can achieve close to 80% processor utilization with as few as three resident threads per processor in a large-scale cache-based machine with an average base network latency of 55 cycles.<>
用于多处理的处理器体系结构
本文描述了一个名为APRIL的快速上下文切换处理器的体系结构,它支持细粒度线程和同步。四月实现了高单线程性能,并支持虚拟动态线程。本文描述了一种基于商用精简指令集计算机(RISC)的APRIL实现和一种可以在大约10个周期内切换上下文的运行时软件系统。在APRIL模拟器上对几个并行应用程序进行的测量表明,与Encore multiax上的相应实现相比,支持基于期货的并行任务的开销减少了2倍。利用性能模型探讨了基于APRIL的多处理器的可扩展性。作者表明,在大型基于缓存的机器上,基于sparc的APRIL实现可以实现接近80%的处理器利用率,每个处理器只有三个常驻线程,平均基本网络延迟为55个周期。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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