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Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)最新文献

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Reliable NoC architecture utilizing a robust rerouting algorithm 可靠的NoC架构利用一个健壮的路由算法
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580142
Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, M. Fathy, Z. Navabi
{"title":"Reliable NoC architecture utilizing a robust rerouting algorithm","authors":"Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, M. Fathy, Z. Navabi","doi":"10.1109/EWDTS.2008.5580142","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580142","url":null,"abstract":"Moving towards reconfigurability is an approach to increase fault tolerance on System-on-Chip design. In this paper, we propose a self-reconfigurable NoC architecture utilizing a robust rerouting method. At first, an offline test strategy for locating system-level faults in NoC switch ports is utilized. Using the information achieved in the test phase, every switch reconfigures itself to avoid routing packets through faulty links by utilizing our local rerouting method. The proposed rerouting method is evaluated using a Transaction-Level platform. Experimental results show that our proposed rerouting method delivers all the packets in a faulty NoC successfully and has a less communication overhead compared to a pure flooding method.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126865484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
HotSpot : Visualizing dynamic power consumption in RTL designs 热点:可视化RTL设计中的动态功耗
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580137
T. English, K. L. Man, E. Popovici, M. Schellekens
{"title":"HotSpot : Visualizing dynamic power consumption in RTL designs","authors":"T. English, K. L. Man, E. Popovici, M. Schellekens","doi":"10.1109/EWDTS.2008.5580137","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580137","url":null,"abstract":"We propose `HotSpot', a tool for the visualization of dynamic power consumption in RTL designs. Using an RTL simulation, the amount of switching activity at major circuit nodes is determined. This information is annotated onto a custom graph of the circuit in the form of `temperature' colour coding. HotSpot highlights areas in which switching activity (and thereby dynamic power consumption) may be reduced. We survey some existing techniques for dynamic power minimization and discuss how HotSpot may identify opportunities for the application of such techniques at RTL. We believe this could lead to reduced power consumption, faster design turnaround and better design practices in future.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115113248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
SoC software components diagnosis technology SoC软件组件诊断技术
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580135
S. Chumachenko, W. Gharibi, A. Hahanova, A. Sushanov
{"title":"SoC software components diagnosis technology","authors":"S. Chumachenko, W. Gharibi, A. Hahanova, A. Sushanov","doi":"10.1109/EWDTS.2008.5580135","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580135","url":null,"abstract":"A novel approach to evaluation of hardware and software testability, represented in the form of register transfer graph, is proposed. Instances of making of software graph models for their subsequent testing and diagnosis are shown.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123569824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance evaluation of In-Circuit Testing on QCA based circuits 基于QCA的电路在线测试性能评价
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580138
N. Kazemifard, M. Ebrahimpour, M. Azghadi, Mohammad A. Tehrani, K. Navi
{"title":"Performance evaluation of In-Circuit Testing on QCA based circuits","authors":"N. Kazemifard, M. Ebrahimpour, M. Azghadi, Mohammad A. Tehrani, K. Navi","doi":"10.1109/EWDTS.2008.5580138","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580138","url":null,"abstract":"Quantum-Dot Cellular automata based circuits (QCA) are one of the favorite novel technologies, which operates on binary data at the nanometer-scale; in which logical operations and data movement are accomplished via Columbic interaction rather than electric current flow leading to a very little power dissipation. Since circuits made from QCA devices could provide various “wins” over CMOS, in recent years there has been an influx of QCA-related research. However before implementing every circuit, its testability and reliability must be mentioned. Hence, testing of these devices is our main concern in this paper and we will show how to perform In-Circuit-Testing on them and the differences and difficulties which is caused by the quantum entity of these circuits.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125214931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Diagnosis of SoC faulty memory cells for embedded repair SoC故障记忆细胞的嵌入式修复诊断
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580144
V. Hahanov, E. Litvinova, Karina Krasnoyaruzhskaya, S. Galagan
{"title":"Diagnosis of SoC faulty memory cells for embedded repair","authors":"V. Hahanov, E. Litvinova, Karina Krasnoyaruzhskaya, S. Galagan","doi":"10.1109/EWDTS.2008.5580144","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580144","url":null,"abstract":"A method of optimal memory fault repair that differs from analogs by application of algebra-logical technology of fault covering by two-dimensional memory matrix topology is proposed. It results in obtaining minimal and full solutions for subsequent repair in real time, which is based on utilization of spares in memory rows and columns.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of CMOS sequential standard cells for defect based voltage testing 基于缺陷电压测试的CMOS顺序标准电池的特性
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580155
A. Wielgus, W. Pleskacz
{"title":"Characterization of CMOS sequential standard cells for defect based voltage testing","authors":"A. Wielgus, W. Pleskacz","doi":"10.1109/EWDTS.2008.5580155","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580155","url":null,"abstract":"This paper presents a new characterization methodology of CMOS sequential standard cells for defect based voltage testing. It allows to estimate the probabilities of physical defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, all of found sequences are validated to check their effectiveness in fault covering and the optimal complex test sequence for all detectable faults is constructed. Experimental results for sequential cells from industrial standard cell library are presented.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132937401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Testing the control part of peripheral interfaces 测试外设接口的控制部分
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580157
Slawomir Zielski, J. Sosnowski
{"title":"Testing the control part of peripheral interfaces","authors":"Slawomir Zielski, J. Sosnowski","doi":"10.1109/EWDTS.2008.5580157","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580157","url":null,"abstract":"Testing peripheral interfaces of computers is the challenging problem in the context of their complexity and multi layer structure. This paper presents our experience with a new systematic approach to generate tests for interfaces and check testability features. It was verified for real interfaces.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123031432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automating Hardware/Software partitioning using dependency Graph 使用依赖关系图自动化硬件/软件分区
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580139
S. Malekshahi, Mahshid Sedghi, Z. Navabi
{"title":"Automating Hardware/Software partitioning using dependency Graph","authors":"S. Malekshahi, Mahshid Sedghi, Z. Navabi","doi":"10.1109/EWDTS.2008.5580139","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580139","url":null,"abstract":"Hardware/Software (HW/SW) partitioning is a major step in embedded system design flow. This paper studies a new method of automated HW/SW partitioning. The main goal of this method is to improve performance in terms of the execution time and consumed area. Proposed algorithms are useful for partitioning using a dependency graph. This Graph models complete dependencies and flow of a design. We applied our method to a high-level description of MP3 decoder as a case study. The results show that a performance-improved automatic partitioning can be achieved using this method.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121939274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Coverage-directed verification of microprocessor units based on cycle-accurate contract specifications 基于周期精确合同规格的微处理器单元的覆盖定向验证
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580153
A. Kamkin
{"title":"Coverage-directed verification of microprocessor units based on cycle-accurate contract specifications","authors":"A. Kamkin","doi":"10.1109/EWDTS.2008.5580153","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580153","url":null,"abstract":"In this paper we describe a method for simulation-based verification of microprocessor units based on cycle-accurate contract specifications. Such specifications describe behavior of a unit in the form of preconditions and postconditions of microoperations. Test sequence generation is based on traversal of FSM constructed automatically from specifications and test coverage definition. We have successfully applied the method to several units of the industrial MIPS64-compatible microprocessor.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129981202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist 模拟网表原理图生成的分区、平面规划、详细布局和路由技术
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580148
Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna
{"title":"Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist","authors":"Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna","doi":"10.1109/EWDTS.2008.5580148","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580148","url":null,"abstract":"The schematic generator has become a very powerful debug tool in EDA in all of the flows whether it is RTL, Synthesis, formal verification or at the layout level. The paper talks about various challenges in showing a \"good\" schematic for a spice netlist and then proposes novel algorithms used to generate the schematic. The paper also links various schematic generation stages with techniques used by P&R tools such as floor planning, global routing, and detailed placement and routing. The transistor level schematic generation differs from the gate level schematic, in that a set of transistors in spice netlist forms a logic and these set of transistors need to be placed together in some symmetry to represent the logic. The paper addresses the challenges that lie in placing and extracting these components which represent logic or a current flow or cascade effect.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122606859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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