Characterization of CMOS sequential standard cells for defect based voltage testing

Abstract

This paper presents a new characterization methodology of CMOS sequential standard cells for defect based voltage testing. It allows to estimate the probabilities of physical defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, all of found sequences are validated to check their effectiveness in fault covering and the optimal complex test sequence for all detectable faults is constructed. Experimental results for sequential cells from industrial standard cell library are presented.