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Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)最新文献

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Multidimensional loop fusion for low-power 低功耗多维回路融合
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580154
D. Lazorenko
{"title":"Multidimensional loop fusion for low-power","authors":"D. Lazorenko","doi":"10.1109/EWDTS.2008.5580154","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580154","url":null,"abstract":"Development of semiconductor technology has led to advent of complex digital systems, such as portable, embedded, SoCs, and FPGA devices. Complexity of modern applications and deep-submicron technologies make low-power design attitude compulsory. The higher the level of abstraction of a design that power optimizations are applied, the higher are potential savings. Memory is known to be extremely power consuming. A new technique of loop fusion to optimize a behavioral description of an application before the hardware/software partitioning is presented in this paper.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124852639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel timing-driven placement algorithm using smooth timing analysis 一种新的基于平滑时序分析的时序驱动布局算法
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580152
A. Ayupov, Leonid Kraginskiy
{"title":"A novel timing-driven placement algorithm using smooth timing analysis","authors":"A. Ayupov, Leonid Kraginskiy","doi":"10.1109/EWDTS.2008.5580152","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580152","url":null,"abstract":"This work proposes a timing-driven placement algorithm that uses a new type of timing analysis, which we call smooth timing analysis. It constructs the timing cost function as a smooth function of cell placement. In addition, for net modeling the algorithm uses a companion net routing that provides more accurate wire delay. The placement task is then formulated as a non-linear optimization problem. Experiments prove that the proposed method is applicable to build timing-driven placement solutions for designs with thousands critical cells. Experimental results on blocks from recent microprocessor designs show a 65% average improvement in total negative slack comparing to a leading industrial flow.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129897106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An IEEE 1500 compatible wrapper architecture for testing cores at transaction level 一个IEEE 1500兼容的封装架构，用于在事务级别测试核心
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580141
F. Refan, P. Prinetto, Z. Navabi
{"title":"An IEEE 1500 compatible wrapper architecture for testing cores at transaction level","authors":"F. Refan, P. Prinetto, Z. Navabi","doi":"10.1109/EWDTS.2008.5580141","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580141","url":null,"abstract":"With the evolution of Electronic System Level (ESL) design methodologies, Transaction Level Modeling (TLM) is regarded as the next step in the direction of system level design. This requires definition of appropriate test strategies at this level including wrapper, scheduling and Test Access Mechanism (TAM) design. In this paper we propose a wrapper for core testing at transaction level, compatible with IEEE 1500 standard architecture. The proposed wrapper is designed to support communication with tlm_fifo as the basic primitive channel of SystemC TLM core. The wrapper is defined as a layer on top of standard IEEE 1500 architecture, including a controller to packetize and depacketize the test stimuli and responses. Controller design, and architecture configuration for serial and parallel core test instructions are presented. Using the same strategy other instructions can be implemented.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An optimized CLP-based technique for generating propagation sequences 一种优化的基于clp的传播序列生成技术
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580150
F. Fummi, V. Guarnieri, C. Marconcini, G. Pravadelli
{"title":"An optimized CLP-based technique for generating propagation sequences","authors":"F. Fummi, V. Guarnieri, C. Marconcini, G. Pravadelli","doi":"10.1109/EWDTS.2008.5580150","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580150","url":null,"abstract":"The paper presents a constraint logic programming-based methodology to generate propagation sequences for functional faults by traversing extended finite state machines. Moreover, different strategies are presented to deal with the state explosion problem arising when constraint logic programming is adopted for solving hard problems. Experimental results show the effectiveness of the proposed solutions.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132142249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An advanced method for synthesizing TLM2-based interfaces 一种基于tlm2的界面合成方法
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580156
N. Hatami, Z. Navabi
{"title":"An advanced method for synthesizing TLM2-based interfaces","authors":"N. Hatami, Z. Navabi","doi":"10.1109/EWDTS.2008.5580156","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580156","url":null,"abstract":"Transaction Level Modeling (TLM) describes system on chips at a high abstraction level in which simulation is faster than the traditional design flow. TLM2 serves the designer with three distinct coding styles among which the untimed style has the best simulation speed with the lowest accuracy. In this paper, we are presenting a method of synthesizing TLM untimed descriptions directly to synthesizable behavioral description from which they can be converted to RTL. This direct mapping skips the intermediate synthesis steps and speed up the design process. We restrict our proposed method to TLM interfaces and specifically work on DMA devices as a common interface in communications sharing a common bus between a processor and its I/O devices.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123811565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Parity prediction method for on-line testing of a Barrel-shifter 桶移器在线测试的奇偶预测方法
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580162
A. Drozd, S. Antoshchuk, A. Rucinski, A. Martinuk
{"title":"Parity prediction method for on-line testing of a Barrel-shifter","authors":"A. Drozd, S. Antoshchuk, A. Rucinski, A. Martinuk","doi":"10.1109/EWDTS.2008.5580162","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580162","url":null,"abstract":"This paper addresses the problem of on-line testing of floating-point computing circuits. The problem is connected with the use of the truncated operations in the part of mantissas processing. The arithmetic shift performed on a Barrel-shifter is the most often used truncated operation. Known approaches to on-line testing of the Barrel-shifter are based on duplication of the truncated operation or on its restoring to a long shift. This makes of the error detection scheme more complex. Known residue checking method, which implements a prior computation of the check results for all causes of a shift reduces the check hardware overhead from square dependence on an operand size to a linear one. However this method requires to perform a series of complex operations for generating and processing of the check codes by modulo. We propose the parity prediction method that significantly simplifies the error detection scheme of a Barrel-shifter by using simple check operations.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On macroplaces in Petri nets Petri网中的宏位
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580151
A. Karatkevich
{"title":"On macroplaces in Petri nets","authors":"A. Karatkevich","doi":"10.1109/EWDTS.2008.5580151","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580151","url":null,"abstract":"This article deals with hierarchical decomposition of Petri nets. The following question is considered: which conditions a subnet should satisfy to make possible its replacement by a macroplace? A general class of such subnets is defined. The theoretical results related to such kind of decomposition are presented. Application of the decomposition to verification of systems, which are specified by means of Petri nets, is considered.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114979115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Digital lock detector for PLL 锁相环数字锁检测器
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580147
Vazgen Melikyan, A. Hovsepyan, M. Ishkhanyan, Tigran Hakobyan
{"title":"Digital lock detector for PLL","authors":"Vazgen Melikyan, A. Hovsepyan, M. Ishkhanyan, Tigran Hakobyan","doi":"10.1109/EWDTS.2008.5580147","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580147","url":null,"abstract":"The purpose of this work is to add one more circuit into the traditional PLL to define the lock condition. Fully digital lock detector is presented. Presented circuit provides a simple design, process independence and design automation.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Concurrent processes synchronisation in statecharts for FPGA implementation FPGA实现的状态图中的并发进程同步
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580158
Grzegorz Labiak, M. Adamski
{"title":"Concurrent processes synchronisation in statecharts for FPGA implementation","authors":"Grzegorz Labiak, M. Adamski","doi":"10.1109/EWDTS.2008.5580158","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580158","url":null,"abstract":"In this paper useful methods of concurrent processes synchronization in UML state machine diagrams are presented. It is not easy to transform complex behaviour description into statecharts, even if the formal specification has already been given, for example as a hierarchical Petri net. Both graphical forms of specifications can be used simultaneously, especially when overlapped concurrent processes are considered. The authors specify the behaviour of an industrial chemical controller as a case study to demonstrate the way of transforming the verbal specification through a formal Petri net model into the UML format, which is more and more frequently understood and widely accepted by industry. The diversification of description gives a chance that the obtained design result, which can be seen both from theoretical and practical points of view, will be correct. The specification is considered from a reconfigurable hardware implementation side and a digital design methodology. It is based on hierarchical concurrent state machine implementation through state encoding into mapping into FPGA matrices, supported by hardware description languages, for example VHDL. In the paper some effective process synchronization methods are included: by introducing global variables and using UML graphical synch states accepted by the UML standard. The proposed methodology is fully supported by system HiCoS, developed at the University of Zielona Góra for a rapid prototyping of reconfigurable logic controllers.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124015781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
System level hardware design and simulation with SystemAda 系统级硬件设计与仿真
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1145/1541788.1541789
Negin Mahani, Parnian Mokri, Z. Navabi
{"title":"System level hardware design and simulation with SystemAda","authors":"Negin Mahani, Parnian Mokri, Z. Navabi","doi":"10.1145/1541788.1541789","DOIUrl":"https://doi.org/10.1145/1541788.1541789","url":null,"abstract":"Recent research in the system level design field has produced a number of techniques for structuring the understanding of systems. Many of these techniques produce design structures that are easily expressible in Ada language. Ada language has a structure which allows the design of systems to be expressed independently of its implementation and thus can be a good system design language to use with these techniques. This paper describes how to use Ada as a system description language like SystemC, which will use Ada compilers (such as Gnat) to evaluate the written program as a system; we have named it, SystemAda. This paper reviews Ada programming language requirements for modeling system behavior and structures at Transaction Level Modeling (TLM). This paper considers possible approaches for extending Ada to meet these requirements.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131889614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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