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Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)最新文献

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Vector-logical diagnosis method for SOC functionalities SOC功能的向量逻辑诊断方法
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580136
V. Hahanov, O. Guz, N. Kulbakova, M. Davydov
{"title":"Vector-logical diagnosis method for SOC functionalities","authors":"V. Hahanov, O. Guz, N. Kulbakova, M. Davydov","doi":"10.1109/EWDTS.2008.5580136","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580136","url":null,"abstract":"Models and methods of vector-logical diagnosis of SoC functionalities in real time are proposed. Algebra-logical procedures of embedded fault diagnosis by means of DNF synthesis that forms all functionality diagnosis solutions are described. The method is based on use the fault detection table that is result of fault simulation.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115389386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test suite consistency verification 测试套件一致性验证
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580145
S. Boroday, A. Petrenko, A. Ulrich
{"title":"Test suite consistency verification","authors":"S. Boroday, A. Petrenko, A. Ulrich","doi":"10.1109/EWDTS.2008.5580145","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580145","url":null,"abstract":"Test cases are themselves prone to errors, thus techniques and tools to validate tests are needed. In this paper, we suggest a method to check mutual consistency of tests in a test suite.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131018325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Utilizing HDL simulation engines for accelerating design and test processes 利用HDL仿真引擎加速设计和测试过程
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580143
Najmeh Farajipour, S. Hosseini, Z. Navabi
{"title":"Utilizing HDL simulation engines for accelerating design and test processes","authors":"Najmeh Farajipour, S. Hosseini, Z. Navabi","doi":"10.1109/EWDTS.2008.5580143","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580143","url":null,"abstract":"This paper introduces a complete test package in VHDL that makes it possible to simulate faults and generate test patterns for a component during its design process. Different approaches on test applications can be combined and then be applied to combinational, sequential and scan-based circuits in a fully configurable and convenient environment. To reveal the capabilities of VHDL in test configurations, we used two different approaches for fault simulation and evaluated them with random tests.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Testability analysis method for hardware and software based on assertion libraries 基于断言库的硬件和软件可测试性分析方法
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580146
M. Kaminska, Roman Prikhodchenko, Artem Kubirya, Pavel Mocar
{"title":"Testability analysis method for hardware and software based on assertion libraries","authors":"M. Kaminska, Roman Prikhodchenko, Artem Kubirya, Pavel Mocar","doi":"10.1109/EWDTS.2008.5580146","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580146","url":null,"abstract":"Testability analysis method for software and hardware products, which represented by system level as a composition of control and operational automata is offered. Methodology of bottlenecks selection for assertions implementation in program code is proposed.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"14 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134290194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RTL-TLM equivalence checking based on simulation 基于仿真的RTL-TLM等价性检验
Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08) Pub Date : 2008-10-01 DOI: 10.1109/EWDTS.2008.5580149
N. Bombieri, F. Fummi, G. Pravadelli
{"title":"RTL-TLM equivalence checking based on simulation","authors":"N. Bombieri, F. Fummi, G. Pravadelli","doi":"10.1109/EWDTS.2008.5580149","DOIUrl":"https://doi.org/10.1109/EWDTS.2008.5580149","url":null,"abstract":"The always increasing complexity of digital systems is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at different abstraction levels above RTL. The bottom-up approach is often adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system. In this context, proving the equivalence between a model and its abstracted version is still an open problem. In fact, traditional equivalence definitions and formal equivalence checking methodologies presented in the literature cannot be applied due to the very different internal characteristics of the models. In this paper, we propose a methodology based on simulation which gives two important contributes. Firstly, it relies on a suite of tools to automate as much as possible the equivalence verification process. Then, a more accurate definition of the equivalence concept is proposed by giving two quality measures of stimuli automatically generated for checking the equivalence between the generated TLM and the RTL golden model.","PeriodicalId":292944,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08)","volume":"18 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129272583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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