An IEEE 1500 compatible wrapper architecture for testing cores at transaction level

Abstract

With the evolution of Electronic System Level (ESL) design methodologies, Transaction Level Modeling (TLM) is regarded as the next step in the direction of system level design. This requires definition of appropriate test strategies at this level including wrapper, scheduling and Test Access Mechanism (TAM) design. In this paper we propose a wrapper for core testing at transaction level, compatible with IEEE 1500 standard architecture. The proposed wrapper is designed to support communication with tlm_fifo as the basic primitive channel of SystemC TLM core. The wrapper is defined as a layer on top of standard IEEE 1500 architecture, including a controller to packetize and depacketize the test stimuli and responses. Controller design, and architecture configuration for serial and parallel core test instructions are presented. Using the same strategy other instructions can be implemented.