Electronics ETF最新文献_第5页

Challenges and Opportunities in Applying Semantics to Improve Access Control in the Field of Internet of Things 应用语义改进物联网领域访问控制的挑战与机遇

Electronics ETF Pub Date : 2018-08-08 DOI: 10.7251/ELS1721066S

Riste Stojanov, Vladimir Zdraveski, D. Trajanov

引用次数: 1

Implementing Master Program on Digital Broadcasting and Broadband Technologies 数字广播与宽带技术硕士课程实施

Electronics ETF Pub Date : 2018-08-08 DOI: 10.7251/els1721100i

S. Ilic, M. Petrovic, B. Jaksic, S. Bojanic, P. Spalevic, R. Babić

引用次数: 1

Modular Environment for Development and Characterization of Tunable Energy Harvesting Systems 可调能量收集系统的模块化开发与表征环境

Electronics ETF Pub Date : 2018-08-08 DOI: 10.7251/ELS1721053C

Javier Casatorres-Aguero, O. Nieto-Taladriz

{"title":"Modular Environment for Development and Characterization of Tunable Energy Harvesting Systems","authors":"Javier Casatorres-Aguero, O. Nieto-Taladriz","doi":"10.7251/ELS1721053C","DOIUrl":"https://doi.org/10.7251/ELS1721053C","url":null,"abstract":"This paper presents the design and development process for an electromagnetic self-tuned vibrational energy harvester prototype. Most state-of-the-art publications present non-tunable or manually tunable vibrational energy harvesters, even the market provides some commercial models of these categories for specific applications. On the other hand, self-tuned energy harvesters are yet rarely seen on the research community. The presented work follows the complete process of designing a prototype to work as a second-order oscillatory system in the form of a cantilever. Three different approaches to tune the resonant frequency of the harvester were considered, each based in changing a property of the cantilever that modifies its resonant frequency. Firstly, it was changed the effective vibrating length of the cantilever. Secondly it was introduced an axial load to the system. Then, the use of a dual cantilever wishbone structure was studied as it allows changing the equivalent stiffness of the system. Finally a prototype based on the first strategy was built and tested, including control algorithms for the maximum electrical energy harvesting point tracking which are presented.","PeriodicalId":290965,"journal":{"name":"Electronics ETF","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132372696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High Efficiency Photovoltaic System with Fuzzy Logic Controller 基于模糊控制器的高效光伏系统

Electronics ETF Pub Date : 2018-08-08 DOI: 10.7251/ELS1721060B

B. Blanusa, Z. Ivanovic, B. Dokic

引用次数: 0

Bode Plots Revisited: a Software System for Automated Generation of Piecewise Linear Frequency Response Plots 波德图重访:一个自动生成分段线性频率响应图的软件系统

Electronics ETF Pub Date : 2018-08-08 DOI: 10.7251/ELS1721076P

P. Pejovic, Amela Zeković

{"title":"Bode Plots Revisited: a Software System for Automated Generation of Piecewise Linear Frequency Response Plots","authors":"P. Pejovic, Amela Zeković","doi":"10.7251/ELS1721076P","DOIUrl":"https://doi.org/10.7251/ELS1721076P","url":null,"abstract":"The paper presents an algorithm for automatic generation of piecewise linear Bode plots. The algorithm is complete in the sense it covers for all posible locations of poles and zeros of transfer functions, including unstable poles and poles and zeroes at the imaginary axis. The starting transfer function is factored into a canonical form, and thirteen elementary transfer function types are defined by their canonical forms. The thirteen elementary transfer function types are shown to be derived from just five generic transfer function types, and piecewise linear Bode plots are defined and depicted for all five of the generic types. For all thirteen elementary transfer function types the nodes they introduce in the piecewise linear plots are specified, as well as the algorithms how they affect the node altitudes. Finally, a three stage algorithm that produces both the Bode plots and the exact numerically computed frequency response plots is described. The algorithm is implemented in a command line based program, illustrated in a filter example, and future work directions are indicated, aiming a graphical user interface and integration of the program to a linear system symbolic analysis software suite.","PeriodicalId":290965,"journal":{"name":"Electronics ETF","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129988644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Application of Artificial Neural Networks in Electronics 人工神经网络在电子学中的应用

Electronics ETF Pub Date : 2018-08-08 DOI: 10.7251/ELS1721087A

M. A. Stosovic, V. Litovski

引用次数: 5

A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology 一种基于16nm CMOS技术的新型Domino逻辑

Electronics ETF Pub Date : 1900-01-01 DOI: 10.7251/els1923041s

Anu Mehra, Smita Singhal, U. Tripathi

{"title":"A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology","authors":"Anu Mehra, Smita Singhal, U. Tripathi","doi":"10.7251/els1923041s","DOIUrl":"https://doi.org/10.7251/els1923041s","url":null,"abstract":"Domino logic is a clocked CMOS (Complementary Metal-Oxide Semiconductor) logic with fewer transistors than static CMOS logic. A PMOS (P-type Metal-Oxide Semiconductor) transistor, known as “keeper”, is included in the design to improve the noise tolerance performance and to reduce the leakage current. The aspect ratio i.e. W/L of the keeper (W=width and L=length) is kept low for the correct functionality of the domino logic. This paper proposes a domino logic with modified keeper in order to improve the circuit with respect to power and area as compared to various existing techniques of domino logic i.e. clock delayed domino logic (CDD), high speed domino logic (HSD), multi threshold high speed domino logic (MHSD), clock delayed sleep mode domino logic (CDSMD), sleep switch domino logic (SSDD), PMOS only sleep switch domino logic (PSSDD), reduced delay variations domino logic (RDVD) and Foot Driven Stack Transistor Domino Logic (FDSTDL). The proposed as well as existing domino logics, for 8-input as well as 16-input OR gate in 16nm CMOS technology, are simulated for different values of W/L of keeper with W/L ratio ranging from 1 to 6. The power-delay-product(PDP) of proposed design has improved as compared to the existing designs. For 8-input OR gate and W/L=6, PDP had improved to maximum of 99.99% for CDD and minimum of 38.09% for SSDD.","PeriodicalId":290965,"journal":{"name":"Electronics ETF","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3