2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)最新文献

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Neural Network-based Methods for Microwave Active Device Modeling 基于神经网络的微波有源器件建模方法
Jinyuan Cui, Qi-jun Zhang
{"title":"Neural Network-based Methods for Microwave Active Device Modeling","authors":"Jinyuan Cui, Qi-jun Zhang","doi":"10.1109/BCICTS53451.2022.10051749","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051749","url":null,"abstract":"This paper presents an overview of artificial neural network (ANN)-based methods for microwave active device modeling. Two types of methods are described, i.e., the ANN method and the Neuro-space mapping method. The use of such methods in modeling GaN HEMTs with temperature and trapping effects are highlighted. A review of an advanced neuro-space mapping method using decomposed mapping and related example for GaN HEMT modeling is provided.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121547302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Maximizing Energy Efficiency in Sub-THz Radio Communication and Prospective toward 6G 最大限度地提高亚太赫兹无线电通信的能源效率和展望6G
K. Okada
{"title":"Maximizing Energy Efficiency in Sub-THz Radio Communication and Prospective toward 6G","authors":"K. Okada","doi":"10.1109/BCICTS53451.2022.10051758","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051758","url":null,"abstract":"In this presentation, a 28-GHz phased-array transceiver and 300GHz transceiver realized by 65nm CMOS will be introduced, which are designed for 5G and beyond. The talk concludes with a discussion on future directions of millimeter-wave wireless communication.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115688152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SiGe HBTs for Power Amplifiers in Front-End of Radio Communication Systems 无线通信系统前端功率放大器的SiGe HBTs
A. Joseph, V. Jain, J. Pekarik, Ajay Raman, S. Syed, Liu Hang, N. Cahoon, R. Wolf, V. Vanukuru, Elanchezhian Veeramani, Beng Woon Lim, U. Raghunathan, Qizhi Z. Liu, Y. Ngu
{"title":"SiGe HBTs for Power Amplifiers in Front-End of Radio Communication Systems","authors":"A. Joseph, V. Jain, J. Pekarik, Ajay Raman, S. Syed, Liu Hang, N. Cahoon, R. Wolf, V. Vanukuru, Elanchezhian Veeramani, Beng Woon Lim, U. Raghunathan, Qizhi Z. Liu, Y. Ngu","doi":"10.1109/BCICTS53451.2022.10051743","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051743","url":null,"abstract":"We provide a status and outlook of the Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) for Power Amplifier (PA) applications in the front-end of a wireless LAN that operates below 8GHz and that in a millimeter-wave (mmWave) phased array system operating above 24 GHz. At GlobalFoundries, for addressing WiFi segment, we have four generations of a 350nm SiGe BiCMOS technology in production and the 5th generation in development. Continuous improvements in power density, gain, and ruggedness are desired from these roadmap technologies to keep up with emerging WiFi standards. For mmWave handset and infrastructure applications, the use of phased array has reduced the peak PA power requirements thereby favoring silicon technologies. We discuss the opportunities for SiGe HBTs in improving Gain and PAE, particularly as frequencies scale towards D-band and above.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"497 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131774531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
InP/GaAsSb DHBTs: THz Analog Performance and Record 180-Gb/s 5.5Vppd-Swing PAM-4 DAC-Driver InP/GaAsSb dhbt:太赫兹模拟性能和记录180 gb /s 5.5Vppd-Swing PAM-4 DAC-Driver
C. Bolognesi, A. Arabhavi, R. Hersent, S. Hamzeloui, F. Jorge, X. Wen, M. Riet, M. Luisier, V. Nodjiadjim, F. Ciabattini, C. Mismer, O. Ostinelli, A. Konczykowska
{"title":"InP/GaAsSb DHBTs: THz Analog Performance and Record 180-Gb/s 5.5Vppd-Swing PAM-4 DAC-Driver","authors":"C. Bolognesi, A. Arabhavi, R. Hersent, S. Hamzeloui, F. Jorge, X. Wen, M. Riet, M. Luisier, V. Nodjiadjim, F. Ciabattini, C. Mismer, O. Ostinelli, A. Konczykowska","doi":"10.1109/BCICTS53451.2022.10051763","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051763","url":null,"abstract":"\"Type-II\" InP/GaAsSb DHBTs are the first non-GaInAs -based transistors to show oscillation frequencies > 1 THz with the associated benefits of higher breakdown voltages, low power dissipation, and superior linearity and scaling characteristics. Whereas no large-signal characterization of THz transistors is found in the literature, THz InP/GaAsSb DHBTs display attractive 94 GHz load-pull characteristics, and less aggressively scaled devices achieve record saturated output power and output power density per unit emitter area. The physical advantages of Type-II InP/GaAsSb are reviewed here. Beyond impressive analog small/large-signal performance metrics, we report a record mixed-signal performance for a PAM-4 DAC-driver designed and fabricated at III-V Lab in a 0.7-μm InP/GaAsSb DHBT technology implemented on epitaxial layers grown at ETHZ. The DAC-driver offers an unprecedented 5.5-Vppd 90-GBd (180 Gb/s) differential output swing with high eye diagram quality and over 12-dB gain control capability at a 1.1-W power consumption, leading to a record 3.1-GBd E/O modulator driver figure-of-merit (FoM). PAM-4 operation at 112-Gb (224 Gb/s) is also demonstrated with 3.35-Vppd and 0.6-W dissipation, also with a record 2.6-GBb E/O FoM. A 110 GHz bandwidth linear driver with a 16.7 dB gain and 0.85-W consumption was also implemented in the same technology, enabling a 4.1-Vppd output swing at 100 Gb/s both in PAM-4 and NRZ signaling. The all-around outstanding performance of InP/GaAsSb DHBTs makes them attractive for a wide variety of analog and mixed-signal circuit blocks used in modern telecommunication applications.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132865593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Static Frequency Divider up to 163 GHz in SiGe-BiCMOS Technology SiGe-BiCMOS技术中高达163 GHz的静态分频器
F. Vogelsang, C. Bredendiek, Jan Schopfel, H. Rücker, N. Pohl
{"title":"A Static Frequency Divider up to 163 GHz in SiGe-BiCMOS Technology","authors":"F. Vogelsang, C. Bredendiek, Jan Schopfel, H. Rücker, N. Pohl","doi":"10.1109/BCICTS53451.2022.10051704","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051704","url":null,"abstract":"This work presents a static divide-by-16 in a 130-nm SiGe-BiCMOS technology, aiming to demonstrate the technologies’ potential. A bias network followed by four divide-by-2 stages and an output buffer is designed. The DC power consumption of the first divider stage and the four divider flip flops in static current mode logic (CML) with buffer is 134.3 mW and 396 mW, respectively. The maximum input frequency of the divider is 163 GHz. The corresponding necessary input power at the divider’s bias network is 4.39 dBm. The observed self-oscillating frequency is 110.56 GHz, while the output power at the by-16 output of the divider is around -9 dBm. Moreover, a special focus is set on the accuracy of divider simulations and the influence of parasitic elements compared to measurement results.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132381561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.03 mm2 Inductorless 50 Gb/s Multiplexer for Josephson Arbitrary Waveform Synthesizers 用于约瑟夫森任意波形合成器的0.03 mm2无电感50gb /s多路复用器
Yerzhan Kudabay, V. Issakov
{"title":"A 0.03 mm2 Inductorless 50 Gb/s Multiplexer for Josephson Arbitrary Waveform Synthesizers","authors":"Yerzhan Kudabay, V. Issakov","doi":"10.1109/BCICTS53451.2022.10051700","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051700","url":null,"abstract":"In this paper we present a high-speed 50 Gb/s current mode logic (CML) 2:1 Multiplexer (MUX) for driving of the Josephson Arbitrary Waveform Synthesizers (JAWS). JAWS can be used in quantum physics-related applications. For example, JAWS can be used as a voltage standard in metrology applications or as a reproducible quantum-based microwave signal source to control superconducting qubits in quantum computing. JAWS requires at its input a very long sigma-delta modulated sequence of current pulses, which is translated by the device into a highly accurate quantized analog voltage at its output. In that sense, JAWS can be seen as a quantum-accurate digital-analog converter (DAC). The very long sequence of digital bits is usually divided into several parts and stored in a memory. The parts are read out cyclically, and multiple parallel streams are serialized into a high-speed 50 Gb/s serial data stream using several multiplexer stages, providing the resulted combined control sequence to the JAWS input. The MUX presented in this work is the last stage of a multiplexer chain operating at the highest frequency and interfacing the JAWS. Quantum computers with a large number of qubits require scalable and power-efficient control electronics. To address this concern, we optimized the presented design for low power consumption to fit within a very low available cooling budget. The design is based on a 130 nm SiGe BiCMOS technology and operates from a 3V single supply voltage. The maximum data rate is 50 Gb/s with a 140 mV single-ended voltage swing. This circuit has a miniature core area of 0.03 mm2 and a very low power consumption of 10 mW.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132587767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Linearity Ka-band InP HBT MMIC Amplifier with 19.8:1 IP3/Pdc LFOM at 48 GHz 高线性ka波段InP HBT MMIC放大器,在48 GHz时采用19.8:1 IP3/Pdc LFOM
K. Kobayashi, P. Partyka, T. Howle, Tony Sellas, L. Hayden
{"title":"High Linearity Ka-band InP HBT MMIC Amplifier with 19.8:1 IP3/Pdc LFOM at 48 GHz","authors":"K. Kobayashi, P. Partyka, T. Howle, Tony Sellas, L. Hayden","doi":"10.1109/BCICTS53451.2022.10051744","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051744","url":null,"abstract":"This paper describes the design and measured performance of a linear efficient Ka-band InP DHBT PA with an IP3/Pdc ratio (LFOM) of 19.8:1 at 48 GHz and 14.1:1 at 40 GHz. The MMIC PA is based on an InP DHBT technology with peak fT and fmax of > 300 GHz and > 600 GHz, respectively, and achieves among the best LFOM at Ka-band above 40 GHz from a MMIC matched amplifier. The amplifier is a single stage four-way combined design optimized for a combination of power and PAE at < 2-dB compression. A peak PAE of 30.5% and associated Pout of 22.2 dBm is obtained at 40 GHz. The P1dB is 21.2 dBm with a PAE of 28.3% and a corresponding IP3 of 36.1 dBm. A remarkable IP3-P1dB = 14.9 dB is significantly higher than the~ 10 dB rule of thumb for semiconductors. At 48 GHz, a peak IP3 of 36.6 dBm and LFOM of 19.8:1 is achieved. Under a 200MHz QPSK modulation, linear PAE’s of 17.4-19.5% for EVM linearity of 5% under an optimum bias at 40 GHz was obtained. This work demonstrates among the highest IP3/Pdc LFOMs reported for a MMIC above 40 GHz.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114369059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A D-Band Transceiver with On-Chip Multi-Port Radiators and Leakage Cancellation in 45nm SOI 带片上多端口散热器和45nm SOI泄漏消除的d波段收发器
V. Lammert, M. Leyrer, V. Issakov
{"title":"A D-Band Transceiver with On-Chip Multi-Port Radiators and Leakage Cancellation in 45nm SOI","authors":"V. Lammert, M. Leyrer, V. Issakov","doi":"10.1109/BCICTS53451.2022.10051760","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051760","url":null,"abstract":"In this work, we present a 140 GHz transceiver front-end in 45 nm SOI CMOS technology. The transceiver is intended for FMCW or PMCW radar applications in D-band. The transmitter employs on-antenna and in-air power combining using two multi-feed on-chip slot dipoles to achieve a measured peak EIRP of 15 dBm without the use of backside cavities or dielectric lenses. The receiver is based on a single-feed dual-slot on-chip antenna configuration with a power combining network to partially cancel TX/RX leakage and avoid blocking of the LNA. The proposed transceiver consumes 452 mA from a 1.8V supply and measures 2.5 mm x 2 mm. To the best of the authors’ knowledge, it represents the first transceiver frontend which employs on-antenna- and in-air combining as well as leakage cancellation at D-band frequencies.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114217983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 180-220-GHz, 12.7-dBm peak Psat and 17.3% peak PAE Power Amplifier in 250-nm InP HBT 一个180-220 ghz, 12.7 dbm峰值Psat和17.3%峰值PAE功率放大器在250纳米InP HBT
J. Chien, Wonho Lee, Jim Buckwalter
{"title":"A 180-220-GHz, 12.7-dBm peak Psat and 17.3% peak PAE Power Amplifier in 250-nm InP HBT","authors":"J. Chien, Wonho Lee, Jim Buckwalter","doi":"10.1109/BCICTS53451.2022.10051748","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051748","url":null,"abstract":"We present a single-stage G-band power amplifier (PA) with high power density and high efficiency in a 250-nm Indium Phosphide (InP) technology. A pseudo-differential common-base (CB) stage with neutralization capacitors and low-loss coupled-line balun (CLB) are designed to deliver 8.3-12.7-dBm output power and 7.7-17.3% power-added efficiency (PAE) over 180-220 GHz. The use of compact baluns allows the design to occupy only 0.011mm2 with power density of 1.69 W/mm2. The design achieves the highest published PAE and power density above 200 GHz for solid-state PAs.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127079823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A SiGe D-Band x12 Frequency Multiplier with Gilbert Cell-Based Tripler 基于吉尔伯特单元的三倍器的SiGe d波段x12倍频器
J. Romstadt, Ahmad Zaben, H. Papurcu, K. Aufinger, N. Pohl
{"title":"A SiGe D-Band x12 Frequency Multiplier with Gilbert Cell-Based Tripler","authors":"J. Romstadt, Ahmad Zaben, H. Papurcu, K. Aufinger, N. Pohl","doi":"10.1109/BCICTS53451.2022.10051705","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051705","url":null,"abstract":"The design and measurement results of a fully-integrated x12 frequency multiplier for D-Band applications in Infineon’s 0.13 µm SiGe BiCMOS technology B11HFC are presented. The frequency multiplier consists of active baluns, frequency doublers, distribution networks, amplifiers, and Gilbert cells. To generate a D-Band signal, the frequency of an input signal is first doubled twice and then tripled. The approach used to triple the frequency is to utilize Gilbert cells instead of a push-pull tripler. Overall, the x12 frequency multiplier exhibits a measured 3 dB bandwidth of 37.5 GHz at a center frequency of 136.25 GHz. The variation of the output power is smaller than 9 dB in the entire D-Band. In addition, the measured harmonic rejection is approximately 24.5 dB at the center frequency.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115754686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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