2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)最新文献

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Recovery of Intrinsic Heterojunction Bipolar Transistors Profiles by Neural Networks 用神经网络恢复本征异质结双极晶体管轮廓
Gregoire Caron, A. Juditsky, N. Guitard, D. Céli
{"title":"Recovery of Intrinsic Heterojunction Bipolar Transistors Profiles by Neural Networks","authors":"Gregoire Caron, A. Juditsky, N. Guitard, D. Céli","doi":"10.1109/BCICTS53451.2022.10051699","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051699","url":null,"abstract":"Due to the shrinking size of devices, the calibration process for TCAD simulators is becoming increasingly complex with time mandatory to run simulations steadily increasing. In this work, we propose a Statistical Learning approach to predict Figures of Merit (FoMs) of a Silicon Germanium Heterojunction bipolar transistor (HBT) from its 1D doping and germanium profile. The surrogate model thus built allows to simulate electrical outputs with high precision much faster than traditional simulations. This model is then used to solve the inverse design problem and recover profiles that match target FoMs.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125291560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.4 THz Efficient OOK/FSK Wireless Transmitter Enabling 3 Gbps at 20 meters 0.4太赫兹高效OOK/FSK无线发射机,在20米范围内实现3gbps
Sam Razavian, Sidharth Thomas, M. Hosseini, A. Babakhani
{"title":"A 0.4 THz Efficient OOK/FSK Wireless Transmitter Enabling 3 Gbps at 20 meters","authors":"Sam Razavian, Sidharth Thomas, M. Hosseini, A. Babakhani","doi":"10.1109/BCICTS53451.2022.10051759","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051759","url":null,"abstract":"This article presents a THz transmitter for enabling energy-efficient multi-Gbps medium-range communication links. The design supports on-off keying (OOK) and frequency shift keying (FSK) modulations at a carrier frequency of 390 GHz, and is fabricated in 90 nm SiGe BiCMOS GlobalFoundries process. The transmitter achieves up to 3-Gbps data rate over 20m point-to-point link using 4-inch collimating parabolic mirrors. No bit errors were detected in transmitting 2 M bits at a data rate of 3 Gbps (BER < 0.5 × 10-6). The transmitter chip consumes 70-mW DC power and has an effective isotropic radiated power (EIRP) of 13 dBm.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"190 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123524911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reactively Matched 2-18 GHz Broadband GaN-on-SiC MMIC Driver Amplifier 响应匹配2-18 GHz宽带GaN-on-SiC MMIC驱动放大器
M. Speir, M. Litchfield
{"title":"Reactively Matched 2-18 GHz Broadband GaN-on-SiC MMIC Driver Amplifier","authors":"M. Speir, M. Litchfield","doi":"10.1109/BCICTS53451.2022.10051738","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051738","url":null,"abstract":"The design and measured performance of a 2-18 GHz GaN-on-SiC MMIC driver amplifier is presented. The reactively matched design improves power-added efficiency at mid-compression levels, as compared to distributed amplifiers, where driver amplifiers operate when saturating high power amplifiers. To achieve such bandwidth, an on-chip bias tee became a main focus of the design. The design achieved a small signal gain of 18.7 dB ± 3 dB and a minimum output power of 30 dBm at 3 dB compression, with an associated PAE between 15 and 25 %.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128130033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5-GHz Injection-Locked Delay Cell with 10–25 ns Adjustable Group-Delay in a 130-nm SiGe BiCMOS Technology 基于130纳米SiGe BiCMOS技术的10 - 25ns可调群延迟的5ghz注入锁定延迟单元
A. Nazhad, A. Alizadeh, Milad Frounchi, J. Cressler, B. Bakkaloglu, S. Kiaei
{"title":"A 5-GHz Injection-Locked Delay Cell with 10–25 ns Adjustable Group-Delay in a 130-nm SiGe BiCMOS Technology","authors":"A. Nazhad, A. Alizadeh, Milad Frounchi, J. Cressler, B. Bakkaloglu, S. Kiaei","doi":"10.1109/BCICTS53451.2022.10051727","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051727","url":null,"abstract":"This paper presents an on-chip delay line (DL) unit with an adjustable group delay (GD) between 10 and 25 ns. This active DL is designed based on an injection locked voltage-controlled oscillator (ILVCO) topology, with operation frequency of 5 GHz. Analog GD tuning is achieved through the control voltage of the VCO and the power of the injected signal. The free running phase noise of the DL at 100 KHz and 10 MHz offsets are − 98 and −140 dBc/Hz, respectively, and follows the phase noise of the injected signal in its locked mode. The DL was implemented in a 130-nm SiGe BiCMOS platform, and consumes 1.26 mm2 of silicon area. The power dissipation of the VCO core and buffer stage are 1.68 and 17.7 mW, respectively. To the authors best knowledge, the achieved GD is among the best.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130788005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Geometry scalable compact modeling of GaAs HBTs GaAs HBTs的几何可伸缩紧凑建模
T. Nardmann, P. Kolev, Nick G. M. Tao, M. Schröter
{"title":"Geometry scalable compact modeling of GaAs HBTs","authors":"T. Nardmann, P. Kolev, Nick G. M. Tao, M. Schröter","doi":"10.1109/BCICTS53451.2022.10051750","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051750","url":null,"abstract":"A set of test structures consisting of HBTs with different sizes and contact layouts as well as TLM structures for determining series resistances was fabricated in a GaAs HBT technology. Based on these structures, a fully scalable parameter set for the compact model HICUM was extracted that accurately describes the transistor behavior in a large range of bias and temperature conditions relevant for practical applications.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130795197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Fully Integrated 3.2-4.7GHz Doherty Power Amplifier in 300mm GaN-on-Si Technology 采用300mm GaN-on-Si技术的全集成3.2-4.7GHz多尔蒂功率放大器
Q. Yu, D. Thomson, H. Then, A. Latorre-Rey, M. Radosavljevic, M. Beumer, P. Koirala, N. Thomas, N. Nair, H. Vora, S. Bader, S. Rami
{"title":"A Fully Integrated 3.2-4.7GHz Doherty Power Amplifier in 300mm GaN-on-Si Technology","authors":"Q. Yu, D. Thomson, H. Then, A. Latorre-Rey, M. Radosavljevic, M. Beumer, P. Koirala, N. Thomas, N. Nair, H. Vora, S. Bader, S. Rami","doi":"10.1109/BCICTS53451.2022.10051762","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051762","url":null,"abstract":"This paper presents the design and characterization of a fully integrated wide band Doherty power amplifier (PA) in 300mm GaN-on-Si technology employing CMOS-like PDK, design rules and design methodology. A new Doherty PA architecture using the stacked transistor configuration with equal voltage distribution is implemented in the auxiliary path to improve performance and power utilization factor. A lumped element based Doherty combiner is designed to maximize the bandwidth and to enhance the back-off efficiency. A wide band lumped element based quadrature coupler is also implemented on-chip. This compact Doherty PA (small core area of 1.66mm2) achieves a 1-dB fractional bandwidth of 38% (3.2-4.7GHz) with over 39% efficiency at 6dB power back-off. This is the first demonstration of Watt level RF power amplifier in 300mm GaN-on-Si technology.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sub-100nm GaN/Si MMIC processes for 6G telecommunications 用于6G电信的Sub-100nm GaN/Si MMIC工艺
R. Leblanc, P. Frijlink, M. Rocchi
{"title":"Sub-100nm GaN/Si MMIC processes for 6G telecommunications","authors":"R. Leblanc, P. Frijlink, M. Rocchi","doi":"10.1109/BCICTS53451.2022.10051739","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051739","url":null,"abstract":"In this paper we present the Gallium Nitride on Silicon (GaN/Si) option as compared with the more common Gallium Nitride on Silicon Carbide (GaN/SiC). Electrical and thermal considerations are presented, together with several examples of microwave and millimeter wave MMICs fabricated with the OMMIC GaN/Si process, more than challenging GaN/SiC counterparts while running at similar channel temperature. Running developments such as 40 nm gate length for over 300 GHz Fmax and Enhancement Depletion (E/D) capabilities allowing easier control of multifunction chips will conclude the paper.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 280 GHz (x8) Frequency Multiplier Chain in 250 nm InP HBT Technology 250nm InP HBT技术中280ghz (x8)倍频链
Utku Soylu, A. Alizadeh, M. Seo, M. Rodwell
{"title":"A 280 GHz (x8) Frequency Multiplier Chain in 250 nm InP HBT Technology","authors":"Utku Soylu, A. Alizadeh, M. Seo, M. Rodwell","doi":"10.1109/BCICTS53451.2022.10051696","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051696","url":null,"abstract":"We report a 280 GHz x8 frequency multiplier chain in 250 nm InP HBT technology. Emitter coupled pair in push-push configuration act as a balanced frequency doubler. The x8 frequency multiplier chain consists of three cascaded frequency doublers. Passive transformers are used to generate single-ended to differential conversion. At 280 GHz, the multiplier chain generates -0.6 dBm output power with 3-dB bandwidth of 48 GHz with input power of -2 dBm at 35 GHz. The unwanted harmonics are suppressed by more than 28 dBc over the frequency range of interest. It consumes 112 mW of DC power and occupies 0.4 mm2 of the chip area. To the authors’ knowledge, these results demonstrate record spectral purity for H-band frequency multipliers working around 280 GHz with low DC power consumption.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Multiple Input and Gain Adjustable Phase Detector in 130 nm SiGe BiCMOS Technology 基于130 nm SiGe BiCMOS技术的多输入和增益可调鉴相器
R. Riaz, M. V. Thayyil, J. Wagner, L. Wetzel, D. Prousalis, F. Ellinger
{"title":"A Multiple Input and Gain Adjustable Phase Detector in 130 nm SiGe BiCMOS Technology","authors":"R. Riaz, M. V. Thayyil, J. Wagner, L. Wetzel, D. Prousalis, F. Ellinger","doi":"10.1109/BCICTS53451.2022.10051737","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051737","url":null,"abstract":"Mutual network synchronization of electronic oscillators relies on their bidirectional coupling. Each oscillator receives at least one input signal from another oscillator. However, in most cases there is more than one input. Consequently, the architecture design of the phase-detectors (PD) of phase-locked loop (PLL) needs to be revised to allow for more than one input signal. This work investigates a PD which has three external inputs, in addition to the feedback signal. It is designed and fabricated in 130 nm SiGe BiCMOS technology. The inputs can be fed independently of each other over a wide range of high input frequencies, ranging from 6 GHz to 17 GHz and it’s gain can be adjusted to correct for variations in the PD output characteristics and to control the PLL’s loop gain. It’s architecture is scalable and can be easily modified to accommodate more input signals. Hence, arbitrary network coupling topologies where PLLs receive input from many other nodes in the network can be realized. It enables setting up, e.g., distributed systems of mutually coupled sensors and sustainable analog computers, so called Ising machines.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129644358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Device modeling tools and their application to SiGe HBT development 器件建模工具及其在SiGe HBT开发中的应用
M. Schröter, Markus Müller, M. Krattenmacher
{"title":"Device modeling tools and their application to SiGe HBT development","authors":"M. Schröter, Markus Müller, M. Krattenmacher","doi":"10.1109/BCICTS53451.2022.10051729","DOIUrl":"https://doi.org/10.1109/BCICTS53451.2022.10051729","url":null,"abstract":"The enabling role of device simulation (TCAD) and compact modeling for the structural optimization of SiGe HBTs during process development is discussed. It is shown that employing a Boltzmann and an augmented drift-diffusion solver in combination with a physics-based compact model and geometry scalable parameter extraction can successfully support process development. As application examples, two particular use scenarios are discussed along with practical examples, and corresponding results are presented.","PeriodicalId":289208,"journal":{"name":"2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133473098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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