A 5-GHz Injection-Locked Delay Cell with 10–25 ns Adjustable Group-Delay in a 130-nm SiGe BiCMOS Technology

Abstract

This paper presents an on-chip delay line (DL) unit with an adjustable group delay (GD) between 10 and 25 ns. This active DL is designed based on an injection locked voltage-controlled oscillator (ILVCO) topology, with operation frequency of 5 GHz. Analog GD tuning is achieved through the control voltage of the VCO and the power of the injected signal. The free running phase noise of the DL at 100 KHz and 10 MHz offsets are − 98 and −140 dBc/Hz, respectively, and follows the phase noise of the injected signal in its locked mode. The DL was implemented in a 130-nm SiGe BiCMOS platform, and consumes 1.26 mm2 of silicon area. The power dissipation of the VCO core and buffer stage are 1.68 and 17.7 mW, respectively. To the authors best knowledge, the achieved GD is among the best.