2012 IEEE Workshop on Signal Processing Systems最新文献_第5页

Real-Time FPGA Implementation of Linear Blending Vision Reconstruction Algorithm Using a Spherical Light Field Camera 球面光场相机线性混合视觉重建算法的实时FPGA实现

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.49

Hossein Afshari, Abdulkadir Akin, Vladan Popovic, A. Schmid, Y. Leblebici

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引用次数: 15

Kolmogorov-Smirnov Test for Spectrum Sensing: From the Statistical Test to Energy Detection 光谱传感的Kolmogorov-Smirnov检验:从统计检验到能量检测

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.58

R. Maršálek, K. Povalac

引用次数: 19

Noise-Resistant Mobile Positioning System Based on Code-Aided RSS Estimation 基于编码辅助RSS估计的抗噪声移动定位系统

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.25

Kai-Ting Shr, Li-Hong Huang, Yuan-Hao Huang

引用次数: 0

A Novel Fast High Resolution Music Algorithm 一种新的快速高分辨率音乐算法

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.37

M. Bouri

引用次数: 1

Low Power Sparse Polynomial Equalizer (SPEQ) for Nonlinear Digital Compensation of an Active Anti-Alias Filter 低功耗稀疏多项式均衡器(SPEQ)用于有源抗混叠滤波器的非线性数字补偿

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.45

K. Gettings, Andrew K. Bolstad, Show-Yah Stuart Chen, M. Ericson, B. Miller, M. Vai

引用次数: 8

Exploration of Full HD Media Decoding on SDR Baseband Processor 基于SDR基带处理器的全高清媒体解码探索

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.48

Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, S. Pollin, Jun Yang

{"title":"Exploration of Full HD Media Decoding on SDR Baseband Processor","authors":"Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, S. Pollin, Jun Yang","doi":"10.1109/SiPS.2012.48","DOIUrl":"https://doi.org/10.1109/SiPS.2012.48","url":null,"abstract":"In recent years, many SDR base band processors have been proposed to meet the high performance and programmability requirement for emerging wireless communications. To be able to support hundreds of Mbps or even Gbps wireless communications, such SDR base band processors often have massive parallel computation capability. This promising processing capability may also be exploited for other types of signal processing tasks. Our work explores the feasibility of performing challenging media processing on SDR base band processors. In this paper, we will show exploratory experiments for supporting full HD H.264/AVC media decoding on a recent version of ADRES based SDR base band processor. Two computational dominant tasks, motion compensation and deblocking filter, have been selected to experiment on the processor. These two blocks account about 80% of the total execution time. Since the processor is designed to be wireless domain specific, algorithm and architecture co-optimizations are crucial to make the goal feasible. Results show that, with limited architecture extension, the ADRES based base band processor achieves very competitive performance and efficiency even when compared with several architectures that are specifically optimized for the media decoding.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128418451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Variable Block Size Motion Estimator Design for Scan Rate Up-convertor 扫描速率上变频器的可变块大小运动估计器设计

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.30

Chun-Fu Chen, G. Lee, Jui-Che Wu, Ching-Jui Hsiao, Jun-Yuan Ke

{"title":"Variable Block Size Motion Estimator Design for Scan Rate Up-convertor","authors":"Chun-Fu Chen, G. Lee, Jui-Che Wu, Ching-Jui Hsiao, Jun-Yuan Ke","doi":"10.1109/SiPS.2012.30","DOIUrl":"https://doi.org/10.1109/SiPS.2012.30","url":null,"abstract":"Variable block size motion estimator (VBSME) for scan rate up-convertor (SRUC) based on the algorithm/architecture co-exploration (AAC) design methodology is presented in this paper. Due to the concurrent exploration of both algorithm and architecture, the designed system requires comparatively less computations and hardware cost but is capable of enhancing the accuracy of motion vector (MV) by refining MV from coarse-grained to fine-grained. The proposed algorithm generates the fine-grained MVs to produce the high quality results especially for the videos with high motion. Benefiting from AAC, we back-annotate the architectural information to algorithm to revise the proposed algorithm and then make the proposed algorithm be mapped onto the targeted platform smoothly. Hence, the SRUC system is able to convert the frame rate from 60 fps up to 120 fps at full HD (1920¡Ñ1080) resolution was successfully implemented and verified on field-programmable array gate (FPGA). This SRUC system's performance has been shown to surpass those state-of-arts and its hardware cost is less than the related works as stated in the literature.","PeriodicalId":286060,"journal":{"name":"2012 IEEE Workshop on Signal Processing Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130842804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection 面向实时目标检测的HOG特征提取处理器体系结构研究

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.57

Kosuke Mizuno, Yosuke Terachi, Kenta Takagi, S. Izumi, H. Kawaguchi, M. Yoshimoto

引用次数: 132

Effects of Varying Message Precision in Digit-Online LDPC Decoders 数字在线LDPC解码器中信息精度变化的影响

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-17 DOI: 10.1109/SiPS.2012.32

P. Marshall, V. Gaudet, D. Elliott

引用次数: 3

Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders 低复杂度编码器的简化多级拟循环LDPC码

2012 IEEE Workshop on Signal Processing Systems Pub Date : 2012-10-01 DOI: 10.1109/SiPS.2012.21

A. Mahdi, Vassilis Paliouras

引用次数: 6