Simplified Multi-Level Quasi-Cyclic LDPC Codes for Low-Complexity Encoders

A. Mahdi, Vassilis Paliouras
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引用次数: 6

Abstract

In this paper we propose a parity check matrix construction technique that simplifies the hardware encoders for Multi-Level-Quasi-Cyclic (ML-QC) LDPC codes. The proposed construction method is based on semi-random - ML-QC extension and appropriately selects shifting factors to reduce the density of the inverted matrix used in several encoding algorithms. The construction method derives low-complexity encoders with minimal degradation of error-correction performance, observable at low BER only. Furthermore a VLSI encoding architecture based on the suggested parity-check matrix (PCM) is also introduced. Experimental results show that the complexity of the proposed encoders depends on the density of the binary base matrix. A comparison with random QC codes reveals substantial complexity reduction without performance degradation for cases of practical interest. In fact a hardware complexity reduction by a factor of 7.5 is achieved, combined with the acceleration of the encoder, for certain cases.
低复杂度编码器的简化多级拟循环LDPC码
本文提出了一种奇偶校验矩阵构造技术,简化了多电平准循环LDPC码的硬件编码器。本文提出的构造方法基于半随机ML-QC扩展,并适当选择移位因子来降低几种编码算法中使用的倒矩阵密度。该构造方法得到了低复杂度的编码器,纠错性能的退化最小,只有在低误码率下才能观察到。此外,还介绍了一种基于建议的奇偶校验矩阵(PCM)的VLSI编码结构。实验结果表明,所提出的编码器的复杂度取决于二进制基矩阵的密度。与随机QC代码的比较揭示了在实际情况下,在没有性能下降的情况下大幅降低复杂性。事实上,在某些情况下,结合编码器的加速,硬件复杂性降低了7.5倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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