发布求助
文献互助 智能选刊 最新文献

Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems最新文献

筛选
英文 中文
Bounding average time separations of events in stochastic timed Petri nets with choice 带选择的随机定时Petri网中事件的边界平均时间分离
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761526
A. Xie, Sangyun Kim, P. Beerel
{"title":"Bounding average time separations of events in stochastic timed Petri nets with choice","authors":"A. Xie, Sangyun Kim, P. Beerel","doi":"10.1109/ASYNC.1999.761526","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761526","url":null,"abstract":"This paper presents a technique to estimate the average time separation of events (TSE) in stochastic timed Petri nets that can model time-independent choice and have arbitrary delay distributions associated with places. The approach analyzes finite net unfoldings to derive closed-form expressions for lower and upper bounds on the average TSE, which can be efficiently evaluated using standard statistical methods. The mean of the derived upper and lower bounds thus provides an estimate of the average TSE which has a well-defined error bound. Moreover, we can often make the error arbitrarily small by analyzing larger net unfoldings at the cost of additional run-time. Experiments on several asynchronous systems demonstrate the quality of our estimate and the efficiency of the technique. The experiments include the performance analysis of a full-scale Petri net model of Intel's asynchronous instruction length decoding and steering unit RAPPID containing over 900 transitions and 500 places.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114751888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Theoretical limits on the data dependent performance of asynchronous circuits 异步电路数据依赖性能的理论限制
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761534
D. Kearney
{"title":"Theoretical limits on the data dependent performance of asynchronous circuits","authors":"D. Kearney","doi":"10.1109/ASYNC.1999.761534","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761534","url":null,"abstract":"Speculations about the ability of asynchronous systems to take advantage of the data dependent performance of circuit components have been widespread. Simulations and actual designs have not however provided much confirmation that it is possible to transfer the average case data dependent performance of a single stage into average case performance of a system without paying an unacceptable area penalty in the implementation. Here it is shown that if area*time is chosen as the performance metric to be minimized there are in fact absolute theoretical limits to achieving data dependent performance as compared with synchronous circuits. These limits are shown to arise in two completely different theoretical approaches each of which make few assumptions about the distribution of data dependent delays experienced when the circuit operates. The theoretical approach confirms many of the tradeoffs that designers of data dependent circuits have long suspected.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127953450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Projection: a synthesis technique for concurrent systems 投影:并发系统的一种综合技术
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761528
R. Manohar, Tak-Kwan Lee, Alain J. Martin
{"title":"Projection: a synthesis technique for concurrent systems","authors":"R. Manohar, Tak-Kwan Lee, Alain J. Martin","doi":"10.1109/ASYNC.1999.761528","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761528","url":null,"abstract":"We present a process decomposition technique for the design of pipelined asynchronous circuits. The technique is simple to use, and is based on projecting a program on different sets of variables. We provide conditions under which the technique can be applied, and show how it can be used to decompose complex concurrent programs.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131835279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Timed trace theoretic verification using partial order reduction 利用偏序约简的时间跟踪理论验证
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761527
T. Yoneda, Hiroshi Ryu
{"title":"Timed trace theoretic verification using partial order reduction","authors":"T. Yoneda, Hiroshi Ryu","doi":"10.1109/ASYNC.1999.761527","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761527","url":null,"abstract":"In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A design framework for asynchronous/synchronous circuits based on CHP to HDL translation 基于CHP到HDL转换的异步/同步电路设计框架
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761529
M. Renaudin, P. Vivet, F. Robin
{"title":"A design framework for asynchronous/synchronous circuits based on CHP to HDL translation","authors":"M. Renaudin, P. Vivet, F. Robin","doi":"10.1109/ASYNC.1999.761529","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761529","url":null,"abstract":"An open design framework, which allows mixing asynchronous and synchronous circuit styles, is presented. It is based on the development of a tool called \"CHP/sub 2/VHDL\" which automatically translates CSP-like specifications (Communicating Sequential Processes) into VHDL programs. This work follows two main motivations: (i) to provide the asynchronous circuit designers with a powerful execution/simulation framework mixing high-level CSP descriptions, HDL programs and gate level descriptions, (ii) to give to synchronous designers familiar with existing HDL-based top-down design flows, the opportunity to include clockless circuits in their designs. An extension of the CHP language proposed by A.J. Martin (1990) is presented and its simulation-oriented features are discussed. The \"CHP/sub 2/VHDL\" translator and its software environment are then described. Finally, a significant design experiment is considered to illustrate the efficiency of the design framework.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122050097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Memory faults in asynchronous microprocessors 异步微处理器中的内存故障
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761524
D. Lloyd, J. Garside, D. A. Gilbert
{"title":"Memory faults in asynchronous microprocessors","authors":"D. Lloyd, J. Garside, D. A. Gilbert","doi":"10.1109/ASYNC.1999.761524","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761524","url":null,"abstract":"Although a large number of asynchronous microprocessors have now been designed, relatively few have attempted to handle memory faults. Memory faults create problems for the design of any pipelined system which are exacerbated by the non-deterministic nature of an asynchronous processor. This paper describes these problems as encountered in the design of asynchronous ARM processors and discusses their specific solutions in the AMULET3 processor. Different mechanisms were used, as expedient, to maintain coherency for the various state-holding elements within the processor; these include register renaming and history buffering in addition to resource locking.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129674145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A timing verifier and timing profiler for asynchronous circuits 异步电路的定时验证器和定时分析器
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761519
Per Arne Karlsen, P. T. Røine
{"title":"A timing verifier and timing profiler for asynchronous circuits","authors":"Per Arne Karlsen, P. T. Røine","doi":"10.1109/ASYNC.1999.761519","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761519","url":null,"abstract":"A system for timing verification and timing profiling of asynchronous circuits is presented. A hierarchical netlist is simulated with an ordinary simulator such as HSPICE. Signal transition information is extracted from the simulation results. The system uses this information and the netlist to compare the circuit to generalized signal transition graph specifications by simulating the flow of tokens in the graphs. If a signal makes a transition that is not allowed by the specification, a timing error has occurred. The flow of tokens in the graph is also used to produce timing statistics for the circuit. Based on these statistics, timing optimization can be done in an iterative design process.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125973386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Symbolic time separation of events 事件的象征性时间分离
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761525
T. Amon, H. Hulgaard
{"title":"Symbolic time separation of events","authors":"T. Amon, H. Hulgaard","doi":"10.1109/ASYNC.1999.761525","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761525","url":null,"abstract":"We extend the TSE timing analysis algorithm into the symbolic domain; that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verification. The two main contributions are (1) an iterative algorithm which continuously narrows down the domain of interest and (2) a practical method for reducing the representation of symbolic expressions containing minimizations and maximizations defined for a given domain. We report experimental results for several asynchronous circuits to demonstrate that symbolic analysis is feasible and that the output provided is what a designer (or perhaps a synthesis tool) would often want to know.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121625808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
AMULET3 revealed AMULET3透露
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761522
J. Garside, S. Furber, Shiaw-Horng Chung
{"title":"AMULET3 revealed","authors":"J. Garside, S. Furber, Shiaw-Horng Chung","doi":"10.1109/ASYNC.1999.761522","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761522","url":null,"abstract":"AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (v4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve higher performance without sacrificing the advantages of asynchronous design and some new power-saving features have been incorporated. This paper outlines the AMULET3 microprocessor core, highlighting where this design differs from its predecessors. Most notable among the changes are the use of a Harvard architecture to increase memory bandwidth and the inclusion of a recorder buffer to handle data forwarding and memory faults.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130756166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Verification of delayed-reset domino circuits using ATACS 用ATACS验证延迟复位多米诺电路
Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI: 10.1109/ASYNC.1999.761518
W. Belluomini, C. Myers, H. P. Hofstee
{"title":"Verification of delayed-reset domino circuits using ATACS","authors":"W. Belluomini, C. Myers, H. P. Hofstee","doi":"10.1109/ASYNC.1999.761518","DOIUrl":"https://doi.org/10.1109/ASYNC.1999.761518","url":null,"abstract":"This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the self-resetting style since internally, a block of self-resetting or delayed-reset domino logic is asynchronous. The circuits are represented using timed event/level structures. These structures correspond very directly to gate level circuits, making the translation from a transistor schematic to a TEL structure straightforward. The state-space explosion problem is mitigated using an algorithm based on partially ordered sets (POSETs). Results on a number of circuits from the recently published guTS (gigahertz unit Test Site) processor from IBM indicate that modules of significant size can be verified with ATACS using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance.","PeriodicalId":285714,"journal":{"name":"Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"2 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114026847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信