利用偏序约简的时间跟踪理论验证

Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems Pub Date : 1999-04-19 DOI:10.1109/ASYNC.1999.761527

T. Yoneda, Hiroshi Ryu

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引用次数: 28

摘要

本文对迹理论验证方法进行了偏序约简的扩展，使之能较好地处理定时电路和定时规格。偏序约简算法是由顽固集方法的时间版本得到的。STARI电路的实验结果表明，该方法是有效的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Timed trace theoretic verification using partial order reduction

In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently.

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Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems

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