A design framework for asynchronous/synchronous circuits based on CHP to HDL translation

An open design framework, which allows mixing asynchronous and synchronous circuit styles, is presented. It is based on the development of a tool called "CHP/sub 2/VHDL" which automatically translates CSP-like specifications (Communicating Sequential Processes) into VHDL programs. This work follows two main motivations: (i) to provide the asynchronous circuit designers with a powerful execution/simulation framework mixing high-level CSP descriptions, HDL programs and gate level descriptions, (ii) to give to synchronous designers familiar with existing HDL-based top-down design flows, the opportunity to include clockless circuits in their designs. An extension of the CHP language proposed by A.J. Martin (1990) is presented and its simulation-oriented features are discussed. The "CHP/sub 2/VHDL" translator and its software environment are then described. Finally, a significant design experiment is considered to illustrate the efficiency of the design framework.