A design framework for asynchronous/synchronous circuits based on CHP to HDL translation

M. Renaudin, P. Vivet, F. Robin
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引用次数: 34

Abstract

An open design framework, which allows mixing asynchronous and synchronous circuit styles, is presented. It is based on the development of a tool called "CHP/sub 2/VHDL" which automatically translates CSP-like specifications (Communicating Sequential Processes) into VHDL programs. This work follows two main motivations: (i) to provide the asynchronous circuit designers with a powerful execution/simulation framework mixing high-level CSP descriptions, HDL programs and gate level descriptions, (ii) to give to synchronous designers familiar with existing HDL-based top-down design flows, the opportunity to include clockless circuits in their designs. An extension of the CHP language proposed by A.J. Martin (1990) is presented and its simulation-oriented features are discussed. The "CHP/sub 2/VHDL" translator and its software environment are then described. Finally, a significant design experiment is considered to illustrate the efficiency of the design framework.
基于CHP到HDL转换的异步/同步电路设计框架
提出了一种允许混合异步和同步电路风格的开放式设计框架。它基于一种名为“CHP/sub 2/VHDL”的工具的开发,该工具可以自动将类似csp的规范(通信顺序过程)转换为VHDL程序。这项工作有两个主要动机:(i)为异步电路设计人员提供一个强大的执行/仿真框架,混合高级CSP描述,HDL程序和门级描述;(ii)为熟悉现有基于HDL的自顶向下设计流程的同步设计人员提供在其设计中包含无时钟电路的机会。提出了A.J. Martin(1990)提出的CHP语言的扩展,并讨论了其面向仿真的特性。然后介绍了“CHP/ sub2 /VHDL”转换器及其软件环境。最后,通过一个重要的设计实验来说明设计框架的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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