K. Degawa, T. Aoki, T. Higuchi, H. Inokawa, Yasuo Takahashi
{"title":"A single-electron-transistor logic gate family and its application - Part I: basic components for binary, multiple-valued and mixed-mode logic","authors":"K. Degawa, T. Aoki, T. Higuchi, H. Inokawa, Yasuo Takahashi","doi":"10.1109/ISMVL.2004.1319952","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319952","url":null,"abstract":"This paper presents a model-based study of an SET (single-electron-transistor) logic gate family for synthesizing binary and MV (multiple-valued) logic circuits. The use of SETs combined with MOS transistors allows a compact realization of basic logic functions that exhibit periodic transfer characteristics. These basic SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV-mixed logic circuits in a highly flexible manner. As an example, this paper describes the design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128150912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On universality of general reversible multiple-valued logic gates","authors":"P. Kerntopf, M. Perkowski, Mozammel H. A. Khan","doi":"10.1109/ISMVL.2004.1319922","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319922","url":null,"abstract":"A set of p-valued logic gates (primitives) is called universal if an arbitrary p-valued logic function can be realized by a logic circuit built up from a finite number of gates belonging to this set. In this paper, we consider the problem of determining the number of universal single-gate libraries of p-valued reversible logic gates with two inputs and two outputs, under the assumption that constant signals can be applied to an arbitrary number of inputs. We have proved some properties of such gates and established that over 97% of ternary gates are universal.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126232185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Polynomial functions on a central relation","authors":"D. Schweigert","doi":"10.1109/ISMVL.2004.1319948","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319948","url":null,"abstract":"We show that the algebra R=(R; /spl Lambda/, /spl or/_, 0, f~/sub i/(x)(i/spl isin/I)) is central polynomially complete. Every central polynomially complete algebra is finite. The clones on a set can be found of any finite and infinite cardinality.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116124511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Signed digit CMOS (SD-CMOS) logic circuits with static operation","authors":"H. Fukuda","doi":"10.1109/ISMVL.2004.1319931","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319931","url":null,"abstract":"A design is proposed for a voltage-mode signed digit CMOS (SD-CMOS) logic circuit. This circuit can provide stable, static operation with a multi-voltage power supply, and it can be fabricated by applying standard CMOS process technology. Key components based on the proposed circuit design, such as a driver circuit, an inverter circuit, a general CMOS logic circuit, and a D-F/F are described. Each circuit element number, operation speed, and power consumption are examined from the viewpoint of system applications.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132476666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}