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Proceedings. 34th International Symposium on Multiple-Valued Logic最新文献

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A single-electron-transistor logic gate family and its application - Part II: design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions 一个单电子-晶体管逻辑门家族及其应用-第二部分:具有线性求和和多值锁存功能的7-3并行计数器的设计和仿真
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319953
H. Inokawa, Yasuo Takahashi, K. Degawa, T. Aoki, T. Higuchi
{"title":"A single-electron-transistor logic gate family and its application - Part II: design and simulation of a 7-3 parallel counter with linear summation and multiple-valued latch functions","authors":"H. Inokawa, Yasuo Takahashi, K. Degawa, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.2004.1319953","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319953","url":null,"abstract":"Guidelines for designing multi-input multi-output counters, based on a single-electron transistor (SET) logic gate family, are presented. A counter consisting of an inverting adder, latched multiple-valued (MV) quantizer, and periodic literals can be made extremely compact owing to the high functionality of SETs and a specific design that utilizes limited kinds of transistors and does not require SETs with control gates or devices for level shifting. Circuit simulation, using a physics-based SET model, reveals that the counter operates at a moderately high speed and with ultra-low power consumption.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121016356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
On the minimization of multiple-valued input binary-valued output functions [logic synthesis] 多值输入二值输出函数的最小化问题[逻辑综合]
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319962
H. Babu, M. Zaber, Md. Rafiqul Islam, M. Rahman
{"title":"On the minimization of multiple-valued input binary-valued output functions [logic synthesis]","authors":"H. Babu, M. Zaber, Md. Rafiqul Islam, M. Rahman","doi":"10.1109/ISMVL.2004.1319962","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319962","url":null,"abstract":"The success of the local covering approach to multiple-valued input two-valued output (MVITVO) functions minimization depends greatly on the proper choice of the base minterms from the ON set of the new techniques developed to improve the performance of this approach. We have introduced a graph called an enhanced assignment graph (EAG) for the efficient grouping of the Boolean variables. In order to make the best choice of the proper base minterm we have defined a new technique to find the potential canonical cube (PCC) covering it. In this process, we have succeeded in finding out the essential primes efficiently which enhances the total computation time and produces better sum of products (SOP).","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126922372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Automata over MV-algebras [many-valued logic] mv -代数上的自动机[多值逻辑]
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319919
B. Gerla
{"title":"Automata over MV-algebras [many-valued logic]","authors":"B. Gerla","doi":"10.1109/ISMVL.2004.1319919","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319919","url":null,"abstract":"We propose the notion of automata over Lukasiewicz many-valued logic, extending fuzzy automata (E. Santos, Info. and Control, vol.13, p.363-377, 1968). Indeed, W-algebras, i.e., algebraic structures related with many-valued Lukasiewicz logic, are made of two semiring reducts obtained considering the supremum operation together with the Lukasiewicz conjunction and the infimum operation together with Lukasiewicz disjunction. Vice-versa, given two semirings over the same domain, and given an isomorphism between these two algebras, we can set some conditions in order to have an MV-algebra. Following the tradition of semirings, in this paper, we study \"many-valued automata\" and \"many-valued formal languages\" interpreted in Lukasiewicz logic.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127719263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Uniform description of calculi for all t-norm logics 所有t范数逻辑的微积分的统一描述
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319917
S. Aguzzoli
{"title":"Uniform description of calculi for all t-norm logics","authors":"S. Aguzzoli","doi":"10.1109/ISMVL.2004.1319917","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319917","url":null,"abstract":"A t-norm logic L/sub */ is the logic of a standard algebra [0, 1]* = ([0, 1], /sup */, /spl rarr/*, 0), for * being a continuous t-norm and /spl rarr/* its residuum. The notion of canonical t-algebra introduced by Hanikova (Neural Network World, vol.12, p.453-460, 2002) and Esteva-Godo-Montagna (Equational characterization of the subvarieties of BL generated by t-norm algebras), the sets-as-signs approach to many-valued tableau systems by Hahnle (Automated Deduction in Multiple-Valued Logics, Oxford University Press, Oxford, 1994), and finite-valued reduction techniques (S. Aguzzoli et al., Journal of Logic, Language and Information, vol.9, p.5-29, 2000; and S. Aguzzoli et al., Archive for Mathematical Logic, vol.41, p.361-399, 2002) allow us to describe in a uniform way co-NP calculi for all t-norm logics.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Non-deterministic matrices 不确定的矩阵
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319955
A. Avron, I. Lev
{"title":"Non-deterministic matrices","authors":"A. Avron, I. Lev","doi":"10.1109/ISMVL.2004.1319955","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319955","url":null,"abstract":"The ordinary concept of a multiple-valued matrix is generalized by introducing non-deterministic matrices (Nmatrices), in which non-deterministic computations of truth-values are allowed. The induced logics are investigated, and a generalized compactness theorem that applies to all finite Nmatrices is proved. Among the applications, it is shown that some important logics for reasoning under uncertainty can be characterized by finite Nmatrices but not by finite ordinary matrices.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133014250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Reduction of sizes of multi-valued decision diagrams by copy properties 利用复制属性减少多值决策图的大小
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319945
D. Jankovic, R. Stankovic, R. Drechsler
{"title":"Reduction of sizes of multi-valued decision diagrams by copy properties","authors":"D. Jankovic, R. Stankovic, R. Drechsler","doi":"10.1109/ISMVL.2004.1319945","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319945","url":null,"abstract":"Copy decision diagrams (CDDs) are an approach to the reduction of sizes of multi-terminal binary decision diagrams (MTBDDs) by using the copy properties of discrete functions. Functions having different types of copy properties can be efficiently represented by CDDs. Illustrative examples are Walsh and Reed-Muller functions as well as different binary codes. In this paper, we consider an extension of this idea to multi-valued decision diagrams (MDDs). We propose copy MDDs (CMDD) as a modification of MDDs that exploits the copy properties of functions, besides the properties already used in the reduction of MDDs. Experimental results show reduction capabilities of CMDDs.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133828337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Monoids whose centralizer is the least clone 其扶正器是最小克隆的一元群
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319927
Hajime Machida, I. Rosenberg
{"title":"Monoids whose centralizer is the least clone","authors":"Hajime Machida, I. Rosenberg","doi":"10.1109/ISMVL.2004.1319927","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319927","url":null,"abstract":"For a monoid M of k-valued unary functions, the centralizer M* is the set of k-valued multi-variable functions which commute with every function in M. In this paper, we consider the problem of finding monoids whose centralizer is the least clone. First we give a sufficient condition for M to have the least clone as its centralizer and show how it can be applied to some concrete examples of M. Then we use Zadori's theorem to obtain another condition for M to satisfy this property.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130081682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A novel multiple-valued logic design using ballistic carbon nanotube FETs 基于弹道碳纳米管场效应管的新型多值逻辑设计
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319913
A. Raychowdhury, K. Roy
{"title":"A novel multiple-valued logic design using ballistic carbon nanotube FETs","authors":"A. Raychowdhury, K. Roy","doi":"10.1109/ISMVL.2004.1319913","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319913","url":null,"abstract":"This paper presents a novel method of multiple-valued logic design using carbon nanotube FETs (CNFETs). The geometry dependant threshold voltage of these transistors has been used to design a ternary logic family. We have developed a SPICE compatible model of ballistic CNFETs. HSPICE has been used in all simulations and transient as well as dc characteristics have been studied.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133670629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Ultra-fine-grain field-programmable VLSI using multiple-valued source-coupled logic 使用多值源耦合逻辑的超细粒度现场可编程VLSI
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319915
H. Munirul, M. Kameyama
{"title":"Ultra-fine-grain field-programmable VLSI using multiple-valued source-coupled logic","authors":"H. Munirul, M. Kameyama","doi":"10.1109/ISMVL.2004.1319915","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319915","url":null,"abstract":"An ultra-fine-grain field-programmable VLSI processor, using multiple-valued source-coupled logic, called MV-FPVLSI is proposed for implementing special-purpose processors. To reduce the complexity of the interconnection blocks, a bit-serial pipeline architecture is employed. It also involves a program-counter-less processor architecture, based on direct allocation. The MV-FPVLSI consists of cells which are arranged in a 2D mesh array. Unlike a field programmable gate array (FPGA), data transmission occurs only between two adjacent cells and the overall data transmission delay is very small. Each cell consists of programmable multiple-valued-source coupled logic (MVSCL) circuits. Instead of using lookup tables, ultra-fine-grain logic operations can be carried out using MVSCL circuits. Moreover, using the same hardware resources, each cell can be reconfigured to operate as either a logic function, a memory function or a counter function. Additional versatility can be achieved through current-mode operation.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114098316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Three dimensional multiple valued circuits design based on single-electron logic 基于单电子逻辑的三维多值电路设计
Proceedings. 34th International Symposium on Multiple-Valued Logic Pub Date : 2004-05-19 DOI: 10.1109/ISMVL.2004.1319954
S. Yanushkevich, V. Shmerko, L. Guy, D. Lu
{"title":"Three dimensional multiple valued circuits design based on single-electron logic","authors":"S. Yanushkevich, V. Shmerko, L. Guy, D. Lu","doi":"10.1109/ISMVL.2004.1319954","DOIUrl":"https://doi.org/10.1109/ISMVL.2004.1319954","url":null,"abstract":"The three-dimensional (3D) model of a multiple valued network, based on a hypercube-like topology, is proposed. A graph embedding technique is used to design hypercube based structures. It is shown that the hypercube-like topology is a single-electron transistor (SET) technology-oriented solution to the implementation of multiple-valued networks.","PeriodicalId":285497,"journal":{"name":"Proceedings. 34th International Symposium on Multiple-Valued Logic","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122337445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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