Proceedings of the 5th ACM international conference on Embedded software最新文献

{"title":"Deeply embedded XML communication: towards an interoperable and seamless world","authors":"J. Helander","doi":"10.1145/1086228.1086241","DOIUrl":"https://doi.org/10.1145/1086228.1086241","url":null,"abstract":"Current consumer electronics devices do not interoperate and are hard to use. Devices use proprietary, device-specific and inflexible protocols. Resources across device classes, such as personal computers and home appliances cannot be taken advantage of. Even recent efforts to connect sensors into networks concentrate on new, ad-hoc protocols that segregate the low-cost devices into their own little world.If all classes of devices could speak the same language, they could talk directly to each other in ways natural to the application without artificial technical barriers. This would allow easily creating seamless applications that aggregate the capabilities of all the electronics. The interoperation adds value to all the devices.Extensible Markup Language (XML) Web Services were conceived to solve the e-business interoperation problem. After decades of failed attempts with EDI, SNA, DCOM, CORBA, and other similar technologies, XML and its communication specification SOAP has proven itself to be a viable technology. If XML is good for e-business, could it also be good for embedded systems communication?This paper argues that XML and SOAP indeed can be useful in small devices. Solutions to performance questions are available and techniques are outlined here. New unique challenges, such as heterogeneous configuration, privacy and security issues, and real-time requirements (e.g. for gaming) are identified and solutions outlined. A prototype implementation for low-cost microcontrollers is described with numbers included.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115620266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploiting last idle periods of links for network power management","authors":"Feihui Li, Guilin Chen, M. Kandemir, Mustafa Karaköy","doi":"10.1145/1086228.1086253","DOIUrl":"https://doi.org/10.1145/1086228.1086253","url":null,"abstract":"Network power optimization is becoming increasingly important as the sizes of the data manipulated by parallel applications and the complexity of inter-processor data communications are continuously increasing. Several hardware-based schemes have been proposed in the past for reducing network power consumption, either by turning off unused communication links or by lowering voltage/frequency in links with low usage. While the prior research shows that these schemes can be effective in certain cases, they share the common drawback of not being able to predict the link active and idle times very accurately. This paper, instead, proposes a compiler-based scheme that determines the last use of communication links at each loop nest and inserts explicit link turn-off calls in the application source. Specifically, for each loop nest, the compiler inserts a turn-off call per communication link. Each turned-off link is reactivated upon the next access to it. We automated this approach within a parallelizing compiler and applied it to eight array-intensive embedded applications.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121503804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rialto: a bridge between description and implementation of control algorithms for wireless sensor networks","authors":"A. Bonivento, L. Carloni, A. Sangiovanni-Vincentelli","doi":"10.1145/1086228.1086262","DOIUrl":"https://doi.org/10.1145/1086228.1086262","url":null,"abstract":"Rialto is a design framework that allows separating the description of a control application for wireless sensor networks from its physical network implementation. The methodology supported by Rialto consists of two steps: An application is described in a Rialto Model in terms of logical components queries and commands. The description is translated into an internal format called RialtoNet that is used to explore all the possible sequence of queries and commands that the application may lead to. The RialtoNet is executed and a set of constraints on the communication and sensing infrastructure is generated.The semantics of RialtoNet is based on a MoC that takes inspiration from Kahn Process Networks, but blocking rules are conveniently modified to exploit the domain specificity.Our approach offers a clear interface to the application designer as Rialto automatically bridges the gap between application and implementation. Hence, Rialto facilitates the adoption of wireless sensor networks technology in application domains, such as industrial control, where the application designer is not a communication engineer.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130824553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Model-based run-time monitoring of end-to-end deadlines","authors":"Jaswinder Ahluwalia, Ingolf Krüger, W. Phillips, M. Meisinger","doi":"10.1145/1086228.1086248","DOIUrl":"https://doi.org/10.1145/1086228.1086248","url":null,"abstract":"The correct interplay among components in a distributed, reactive system is a crucial development task, particularly for embedded systems such as those in the automotive domain. Model-based development is a promising means for capturing key structural and behavioral requirements before implementing code. Current development approaches focus on components as the central development entity, leaving component integration as a separate and error-prone task in later stages of the system development process. This approach is particularly problematic in the area of Quality-of-Service properties that are inherently end-to-end. We address this problem by using a model where system functions, not components implementing them, are central from the early phases of requirements capture through implementation. We develop a domain model for system functions (or services) based on interaction patterns; this model captures deadline specifications ranging from individual messages to entire services. Using a combination of modeling tools and code-generators for the RT CORBA platform, we provide an experimentation platform for monitoring these specified deadlines in executable specifications.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122073654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pinapa: an extraction tool for SystemC descriptions of systems-on-a-chip","authors":"M. Moy, F. Maraninchi, L. Maillet-Contoz","doi":"10.1145/1086228.1086286","DOIUrl":"https://doi.org/10.1145/1086228.1086286","url":null,"abstract":"SystemC is becoming a de-facto standard for the description of complex systems-on-a-chip. It enables system-level descriptions of SoCs: the same language is used for the description of the architecture, software and hardware parts.A tool like Pinapa is compulsory to work on realistic SoCs designs for anything else than simulation: it is able to extract both architecture and behavior information from SystemC code, with very few limitations. Pinapa can be used as a front-end for various analysis tools, ranging from \"superlint\" to model-checking. It is open source and available from http://greensocs.sourceforge.net/pinapa/. There exists no equivalent tool for SystemC up to now.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"44 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121184166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Passive mid-stream monitoring of real-time properties","authors":"L. Jagadeesan, R. Viswanathan","doi":"10.1145/1086228.1086291","DOIUrl":"https://doi.org/10.1145/1086228.1086291","url":null,"abstract":"Passive monitoring or testing of complex systems and networks running in the field can provide valuable insights into their behavior in actual environments of use. In certain contexts, such as network management and intrusion detection for security, passive monitoring is the most applicable methodology for assuring correctness of the system's behavior. More generally, it can serve to complement and extend functional testing and fault detection efforts that take place during the software/product development lifecycle. Two distinguishing aspects of passive monitoring are that: (a) the fault detection process cannot influence the execution of the system by providing particular inputs to the system, and (b) observations are obtained mid-stream, from an unknown state in the middle of the execution of the system. In this paper, we present results on passively testing for real-time behavioral properties that can be applied to a large class of systems including those that can be modeled as timed automata. Our results provide a natural extension of the passive testing study conducted in [17] for untimed properties. We have implemented our approach using the real-time model checker UPPAAL, and we report on its application to passively test fault tolerance software in a telecommunications switch developed at Lucent Technologies.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133232789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cutpoints for formal equivalence verification of embedded software","authors":"Xiushan Feng, A. Hu","doi":"10.1145/1086228.1086284","DOIUrl":"https://doi.org/10.1145/1086228.1086284","url":null,"abstract":"Like hardware, embedded software faces stringent design constraints, undergoes extremely aggressive optimization, and therefore has a similar need for verifying the functional equivalence of two versions of a design, e.g., before and after an optimization. The concept of cutpoints was a breakthrough in the formal equivalence verification of combinational circuits and is the key enabling technology behind its successful commercialization. We introduce an analogous idea for formally verifying the equivalence of structurally similar, \"combinational\" software, i.e., software routines that compute a result and return/terminate, rather than executing indefinitely. We have implemented a proof-of-concept cutpoint approach in our prototype verification tool for the TI C6x family of VLIW DSPs, and our experiments show large improvements in runtime and memory usage.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123930605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Toward a semantic anchoring infrastructure for domain-specific modeling languages","authors":"Kai Chen, J. Sztipanovits, S. Neema","doi":"10.1145/1086228.1086236","DOIUrl":"https://doi.org/10.1145/1086228.1086236","url":null,"abstract":"Metamodeling facilitates the rapid, inexpensive development of domain-specific modeling languages (DSML-s). However, there are still challenges hindering the wide-scale industrial application of model-based design. One of these unsolved problems is the lack of a practical, effective method for the formal specification of DSML semantics. This problem has negative impact on reusability of DSML-s and analysis tools in domain specific tool chains. To address these issues, we propose a formal well founded methodology with supporting tools to anchor the semantics of DSML-s to precisely defined and validated \"semantic units\". In our methodology, each of the syntactic and semantic DSML components is defined precisely and completely. The main contribution of our approach is that it moves toward an infrastructure for DSML design that integrates formal methods with practical engineering tools. In this paper we use a mathematical model, Abstract State Machines, a common semantic framework to define the semantic domains of DSML-s.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123177933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A unified HW/SW interface model to remove discontinuities between HW and SW design","authors":"A. Bouchhima, X. Chen, F. Pétrot, W. Cesário, A. Jerraya","doi":"10.1145/1086228.1086258","DOIUrl":"https://doi.org/10.1145/1086228.1086258","url":null,"abstract":"One major challenge in System-on-Chip (SoC) design is the definition and design of interfaces between hardware and software. Traditional ASIC designer and software designer model HW/SW interface twice. Using two separate models introduces a discontinuity between hardware and software. This paper introduces a unified HW/SW component model to describe different parts of HW/SW interface at different abstraction levels. The benefits of using the proposed model are two fold: first, it provides a single model to present system design from abstract specification to mixed HW/SW implementation and second, it enables full system simulation at different abstraction level during refinement flow.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128211140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance annotation-aware JVM for Java cards","authors":"A. Azevedo, A. Kejariwal, A. Veidenbaum, A. Nicolau","doi":"10.1145/1086228.1086240","DOIUrl":"https://doi.org/10.1145/1086228.1086240","url":null,"abstract":"Early applications of smart cards have focused in the area of personal security. Recently, there has been an increasing demand for networked, multi-application cards. In this new scenario, enhanced application-specific on-card Java applets and complex cryptographic services are executed through the smart card Java Virtual Machine (JVM). In order to support such computation-intensive applications, contemporary smart cards are designed with built-in microprocessors and memory. As smart cards are highly area-constrained environments with memory, CPU and peripherals competing for a very small die space, the VM execution engine of choice is often a small, slow interpreter. In addition, support for multiple applications and cryptographic services demands high performance VM execution engine. The above necessitates the optimization of the JVM for Java Cards.In this paper we present the concept of an annotation-aware interpreter that optimizes the interpreted execution of Java code using Java bytecode SuperOperators (SOs). SOs are groups of bytecode operations that are executed as a specialized VM instruction. Simultaneous translation of all the bytecode operations in an SO reduces the bytecode dispatch cost and the number of stack accesses (data transfer to/from the Java operand stack) and stack pointer updates. Furthermore, SOs help improve native code quality without hindering class file portability. Annotation attributes in the class files mark the occurrences of valuable SOs, thereby dispensing the expensive task of searching and selecting SOs at runtime. Besides, our annotation-based approach incurs minimal memory overhead as opposed to just-in-time (JIT) compilers.We obtain an average speedup of 18% using an interpreter customized with the top SOs formed from operation folding patterns. Further, we show that greater speedups could be achieved by statically adding to the interpreter application-specific SOs formed by top basic blocks. The effectiveness of our approach is evidenced by performance improvements of (upto) 131% obtained using SOs formed from optimized basic blocks.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114746515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}