{"title":"Distributing synchronous programs using bounded queues","authors":"M. Zennaro, R. Sengupta","doi":"10.1145/1086228.1086287","DOIUrl":"https://doi.org/10.1145/1086228.1086287","url":null,"abstract":"This paper is about the modular compilation and distribution of a sub-class of Simulink programs [9] across networks using bounded FIFO queues. The problem is first addressed mathematically. Then, based on these formal results, a software library for the modular compilation and distribution of Simulink programs is given. The performance of the library is given. The value of synchronous programming for the next generation of traffic control is discussed. The adoption of these tools seems to be the natural candidate to address the needs of traffic engineers. As a case study we present an implementation in Simulink of a controller for coordinated traffic signals in an asymmetric peak hour traffic scenario and we evaluate its computational performance in a distributed environment.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126922598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Random testing of interrupt-driven software","authors":"J. Regehr","doi":"10.1145/1086228.1086282","DOIUrl":"https://doi.org/10.1145/1086228.1086282","url":null,"abstract":"Interrupt-driven embedded software is hard to thoroughly test since it usually contains a very large number of executable paths. Developers can test more of these paths using random interrupt testing---firing random interrupt handlers at random times. Unfortunately, naïve application of random testing to interrupt-driven software does not work: some randomly generated interrupt schedules violate system semantics, causing spurious failures. The contribution of this paper is the design, implementation, and experimental evaluation of RID, a restricted interrupt discipline that hardens embedded software with respect to unexpected interrupts, making it possible to perform random interrupt testing and also protecting it from spurious interrupts after deployment. We evaluate RID by implementing it in TinyOS and then using random interrupt testing to find bugs and also to drive applications toward their worst-case stack depths.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130055097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HAIL: a language for easy and correct device access","authors":"Jun Sun, Wanghong Yuan, M. Kallahalla, N. Islam","doi":"10.1145/1086228.1086230","DOIUrl":"https://doi.org/10.1145/1086228.1086230","url":null,"abstract":"It is difficult to write device drivers. One factor is that writing low-level code for accessing devices and manipulating their registers is tedious and error-prone. For many system-on-chip based systems, buggy hardware, imprecise documentation, and code reuse worsen the situation further. This paper presents HAIL (Hardware Access Interface Language), a language-based approach to simplify device access programming and generate error checking code against bugs in software, hardware, and documentation. HAIL is a domain-specific language that specifies all aspects of a device's programming interface and the access methods in a particular system and OS. A compiler automatically checks the specification and translates it into C code for device access, with optional debugging code. The generated code can be included directly into device driver code. In the paper, we argue that HAIL lowers development effort, incurs minimal runtime overhead, and reduces device access related bugs. We also show that the HAIL specification can be reused for different operating systems, thereby reducing porting costs.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123680051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The formal verification of a reintegration protocol","authors":"Lee Pike, S. Johnson","doi":"10.1145/1086228.1086280","DOIUrl":"https://doi.org/10.1145/1086228.1086280","url":null,"abstract":"We report the first formal verification of a reintegration protocol for a safety-critical distributed embedded system. A reintegration protocol increases system survivability by allowing a transiently-faulty node to regain state. The protocol is verified in the Symbolic Analysis Laboratory (SAL), where bounded model-checking and decision procedures are used to verify infinite-state systems by k-induction. The protocol and its environment are modeled using a recently-developed explicit real-time model. Because k-induction has exponential complexity, we optimize this model to reduce the size of k necessary for the verification and to make $k$ invariant to the number of nodes. A corollary of the verification is that a clique avoidance property is satisfied.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126109084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Albert Cohen, M. Duranton, C. Eisenbeis, C. Pagetti, Florence Plateau, Marc Pouzet
{"title":"Synchronization of periodic clocks","authors":"Albert Cohen, M. Duranton, C. Eisenbeis, C. Pagetti, Florence Plateau, Marc Pouzet","doi":"10.1145/1086228.1086289","DOIUrl":"https://doi.org/10.1145/1086228.1086289","url":null,"abstract":"We propose a programming model dedicated to real-time video-streaming applications for embedded media devices, including high-definition TVs. This model is built on the synchronous programming model extended with domain-specific knowledge --- periodic evolution of streams --- to allow correct-by-construction properties of the application to be proven by the compiler. These properties include buffer requirements and delays between input and output streams.Such properties are tedious to analyze by hand, due to the combinatorics of video filters, multiple data rates and formats. We show how to extend a core synchronous data-flow language with a notion of periodic clocks, and to design a relaxed clock calculus (a type system for clocks) to allow non strictly synchronous processes to be composed. This relaxation is associated with a subtyping rule in the clock calculus. Delay, buffer insertion and control code for these buffers are automatically inferred from the clock types through a systematic program transformation.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114423489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Model-based analysis of distributed real-time embedded system composition","authors":"G. Madl, S. Abdelwahed","doi":"10.1145/1086228.1086294","DOIUrl":"https://doi.org/10.1145/1086228.1086294","url":null,"abstract":"Key challenges in distributed real-time embedded (DRE) system developments include safe composition of system components and mapping the functional specifications onto the target platform. Model-based verification techniques provide a way for the design-time analysis of DRE systems enabling rapid evaluation of design alternatives with respect to given performance measures before committing to a specific platform. This paper introduces a semantic domain for model-based analysis of a general class of DRE systems capturing their key time-based performance measures. We then utilize this semantic domain to develop a verification strategy for preemptive schedulability using available model checking tools. The proposed framework and verification strategy is demonstrated on a mission-critical avionics DRE system case study.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114620177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. F. Bacon, P. Cheng, D. Grove, M. Hind, V. T. Rajan, Eran Yahav, Matthias Hauswirth, C. Kirsch, Daniel Spoonhower, Martin T. Vechev
{"title":"High-level real-time programming in Java","authors":"D. F. Bacon, P. Cheng, D. Grove, M. Hind, V. T. Rajan, Eran Yahav, Matthias Hauswirth, C. Kirsch, Daniel Spoonhower, Martin T. Vechev","doi":"10.1145/1086228.1086242","DOIUrl":"https://doi.org/10.1145/1086228.1086242","url":null,"abstract":"Real-time systems have reached a level of complexity beyond the scaling capability of the low-level or restricted languages traditionally used for real-time programming.While Metronome garbage collection has made it practical to use Java to implement real-time systems, many challenges remain for the construction of complex real-time systems, some specific to the use of Java and others simply due to the change in scale of such systems.The goal of our current research is the creation of a comprehensive Java-based programming environment and methodology for the creation of complex real-time systems. Our goals include construction of a provably correct real-time garbage collector capable of providing worst case latencies of 100 μs, capable of scaling from sensor nodes up to large multiprocessors; specialized programming constructs that retain the safety and simplicity of Java, and yet provide sub-microsecond latencies; the extension of Java's \"write once, run anywhere\" principle from functional correctness to timing behavior; on-line analysis and visualization that aids in the understanding of complex behaviors; and a principled probabilistic analysis methodology for bounding the behavior of the resulting systems.While much remains to be done, this paper describes the progress we have made towards these goals.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124167555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"From statecharts to ESP: programming with events, states and predicates for embedded systems","authors":"V. Sreedhar, M. Marinescu","doi":"10.1145/1086228.1086238","DOIUrl":"https://doi.org/10.1145/1086228.1086238","url":null,"abstract":"Statecharts are probably the most popular mechanism for behavior modeling of embedded system components. Modeling a component involves using a mainstream language for features that statecharts cannot express: detailed behavior of conditions and actions, object-orientation and distributed computing features. Debugging is done at the level of the generated native code. Rather than treating statecharts as a separate programming model from the native programming model, we extend a (Java-like) language with support for key concepts of statecharts: (1) explicit states, (2) asynchronous events, and (3) conditional execution. This paper presents ESP*, a language that supports statecharts and a set of other advanced programming concepts to make programming embedded systems easier. The paper also shows how to translate statecharts to ESP*.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132438541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using de-optimization to re-optimize code","authors":"S. Hines, P. Kulkarni, D. Whalley, J. Davidson","doi":"10.1145/1086228.1086251","DOIUrl":"https://doi.org/10.1145/1086228.1086251","url":null,"abstract":"The nature of embedded systems development places a great deal of importance on meeting strict requirements in areas such as static code size, power consumption, and execution time. In order to meet these requirements, embedded developers frequently generate and tune assembly code for applications by hand, despite the disadvantages of coding at a low level. The phase ordering problem is a well-known problem affecting the design of optimizing compilers. Hand-tuned code is susceptible to an analogous problem to phase ordering due to the process of iterative refinement, but there has been little research in mitigating its effect on the quality of the generated code. This paper presents an extension of the VISTA framework for investigating the effect and potential benefit of performing de-optimization before re-optimizing assembly code. The design and implementation of algorithms for de-optimization of both loop-invariant code motion and register allocation, along with results of experiments regarding de-optimization and re-optimization of previously generated assembly code are also presented.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123483048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Rothbart, U. Neffe, C. Steger, R. Weiss, E. Rieger, Andreas Mühlberger
{"title":"Power consumption profile analysis for security attack simulation in smart cards at high abstraction level","authors":"K. Rothbart, U. Neffe, C. Steger, R. Weiss, E. Rieger, Andreas Mühlberger","doi":"10.1145/1086228.1086268","DOIUrl":"https://doi.org/10.1145/1086228.1086268","url":null,"abstract":"Smart cards are embedded systems which are used in an increasing number of secure applications. As they store and deal with confidential and secret data many attacks are performed on these cards to reveal this private information. Consequently, the security demands on smart cards are very high. It is mandatory to evaluate the security of the design but this is performed often very late in the design process or when the chip has already been manufactured. This paper presents a hierarchical security attack simulation flow for smart card designs where security attacks can be simulated in the processor specific model at transaction layer 1 in SystemC. Therefore, the power consumption profile is analyzed at this level. Preliminary results show that this analysis at high abstraction level can be used to determine vulnerabilities of the system to security attacks. Moreover, points to insert software countermeasures can easily be identified.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}