Proceedings of the 5th ACM international conference on Embedded software最新文献_第2页

Tag machines 标签的机器

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086276

A. Benveniste, B. Caillaud, L. Carloni, A. Sangiovanni-Vincentelli

引用次数: 34

A conservative extension of synchronous data-flow with state machines 使用状态机的同步数据流的保守扩展

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086261

Jean-Louis Colaço, B. Pagano, Marc Pouzet

{"title":"A conservative extension of synchronous data-flow with state machines","authors":"Jean-Louis Colaço, B. Pagano, Marc Pouzet","doi":"10.1145/1086228.1086261","DOIUrl":"https://doi.org/10.1145/1086228.1086261","url":null,"abstract":"This paper presents an extension of a synchronous data-flow language such as Lustre with imperative features expressed in terms of powerful state machine à la SyncChart. This extension is fully conservative in the sense that all the programs from the basic language still make sense in the extended language and their semantics is preserved.From a syntactical point of view this extension consists in hierarchical state machines that may carry at each hierarchy level a bunch of equations. This proposition is an alternative to the joint use of Simulink and Stateflow but improves it by allowing a fine grain mix of both styles.The central idea of the paper is to base this extension on the use of clocks, translating imperative constructs into well clocked data-flow programs from the basic language. This clock directed approach is an easy way to define a semantics for the extension, it is light to implement in an existing compiler and experiments show that the generated code compete favorably with ad-hoc techniques. The proposed extension has been implemented in the ReLuC compiler of Scade/Lustre and in the Lucid Synchrone compiler.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121401926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 147

1 + ε approximation clock rate assignment for periodic real-time tasks on a voltage-scaling processor 电压缩放处理器上周期性实时任务的1 + ε近似时钟速率分配

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086273

Jian-Jia Chen, Tei-Wei Kuo, C. Shih

引用次数: 42

Communication strategies for shared-bus embedded multiprocessors 共享总线嵌入式多处理器的通信策略

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086233

N. Bambha, S. Bhattacharyya

引用次数: 4

A GA-based scheduling method for FlexRay systems FlexRay系统的ga调度方法

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086249

Shan Ding, Naohiko Murakami, H. Tomiyama, H. Takada

引用次数: 51

Session details: Panel 1 会议详情:面板1

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/3240508.3286933

D. D. Gajski, Grant Martin

引用次数: 0

AutoDVS: an automatic, general-purpose, dynamic clock scheduling system for hand-held devices AutoDVS:用于手持设备的自动、通用、动态时钟调度系统

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086270

Selim Gurun, C. Krintz

引用次数: 16

Session details: Panel 2 会议详情:小组2

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/3240508.3286937

J. Sztipanovitz

引用次数: 0

A formal approach to fault tree synthesis for the analysis of distributed fault tolerant systems 分布式容错系统故障树综合的形式化方法

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086272

Mark L. McKelvin, G. Eirea, C. Pinello, Sri Kanajan, A. Sangiovanni-Vincentelli

{"title":"A formal approach to fault tree synthesis for the analysis of distributed fault tolerant systems","authors":"Mark L. McKelvin, G. Eirea, C. Pinello, Sri Kanajan, A. Sangiovanni-Vincentelli","doi":"10.1145/1086228.1086272","DOIUrl":"https://doi.org/10.1145/1086228.1086272","url":null,"abstract":"Designing cost-sensitive real-time control systems for safety-critical applications requires a careful analysis of both performance versus cost aspects and fault coverage of fault tolerant solutions. This further complicates the difficult task of deploying the embedded software that implements the control algorithms on a possibly distributed execution platform (for instance in automotive applications). In this paper, we present a novel technique for constructing a fault tree that models how component faults may lead to system failure. The fault tree enables us to use existing commercial analysis tools to assess a number of dependability metrics of the system. Our approach is centered on a model of computation, Fault Tolerant Data Flow (FTDF), that enables the integration of formal verification techniques. This new analysis capability is added to an existing design framework, also based on FTDF, that enables a synthesis-based, correct-by-construction, design methodology for the deployment of real-time feedback control systems in safety critical applications.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124519566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Compiler-guided register reliability improvement against soft errors 针对软错误的编译器引导的寄存器可靠性改进

Proceedings of the 5th ACM international conference on Embedded software Pub Date : 2005-09-18 DOI: 10.1145/1086228.1086266

Jun Yan, Wei Zhang

{"title":"Compiler-guided register reliability improvement against soft errors","authors":"Jun Yan, Wei Zhang","doi":"10.1145/1086228.1086266","DOIUrl":"https://doi.org/10.1145/1086228.1086266","url":null,"abstract":"With the scaling of technology, transient errors caused by external particle strikes have become a critical challenge for microprocessor design. As embedded processors are widely used in reliability-sensitive environments, it becomes increasingly important to develop cost-effective techniques to improve the processor reliability against soft errors. This paper focuses on studying the register file immunity against soft errors since modern processors typically employ a large number of registers, which are accessed very frequently. As a result, soft errors occurred in registers can easily propagate to functional units or the memory system, leading to silent data error (SDC) or system crash.To develop cost-effective techniques to fight soft errors for embedded processors, the first step is to understand the register file susceptibility to soft errors and its impact on the system reliability accurately. Toward this goal, this paper proposes the concept of register vulnerability factor (RVF) to characterize the probability that register transient errors can escape the register file and thus potentially impact the system reliability. Built upon the RVF concept, we then propose two cost-effective compiler-guided techniques to improve the register file reliability by lowering the RVF value. Our experiments indicate that on average, the RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly while protecting register files against transient errors.","PeriodicalId":284648,"journal":{"name":"Proceedings of the 5th ACM international conference on Embedded software","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124588310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 79