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2012 IEEE International Symposium on Circuits and Systems最新文献

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Noise canceling chopper stabilized front-end for electrochemical biosensors with improved dynamic range 改进动态范围的电化学生物传感器消噪斩波稳定前端
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-08-20 DOI: 10.1109/ISCAS.2012.6271731
Viswanathan Balasubramanian, Pierre-François Ruedi, C. Enz
{"title":"Noise canceling chopper stabilized front-end for electrochemical biosensors with improved dynamic range","authors":"Viswanathan Balasubramanian, Pierre-François Ruedi, C. Enz","doi":"10.1109/ISCAS.2012.6271731","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271731","url":null,"abstract":"This paper presents a front-end circuit for electrochemical biosensors used in applications like DNA sensing. Novelty in this work lies in the front-end architecture which uses noise canceling (NC) combined with chopper stabilization (CS) for rejecting 1/f noise and to our knowledge, a front-end using the principle of noise canceling for 1/f noise rejection has not been reported. Motivation for using this front-end are: 1) The circuit exhibits low noise performance with its sensitivity not being limited by 1/f noise thanks to noise canceling and chopping. 2) The canceling property in this topology is used effectively to achieve improved linearity and higher dynamic range (DR) in addition to 1/f noise rejection. The fully differential front-end circuit is designed in 0.18 μm CMOS process and consumes 46 μA while operating on 1.8 V supply voltage. Based on the simulation results, a DR improvement of greater than 10 dB is achieved by the use of canceling technique.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125845557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A neuromorphic VLSI grid cell system 一种神经形态的VLSI网格细胞系统
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6271787
Tarek M. Massoud, T. Horiuchi
{"title":"A neuromorphic VLSI grid cell system","authors":"Tarek M. Massoud, T. Horiuchi","doi":"10.1109/ISCAS.2012.6271787","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271787","url":null,"abstract":"Neurons in the medial entorhinal cortex of rats have been found to respond in a two-dimensional hexagonal “grid” pattern anchored to the environment. “Grid cells” with different spatial frequencies are thought to contribute to the creation of unimodal “place” cell responses useful for spatial navigation. In this paper we present results from an analog VLSI circuit that generates a hexagonal grid of activity using continuous attractor dynamics and transmits this pattern via neuron-like spikes. This circuit is a component of a larger system for modeling the neural circuits underlying mammalian spatial navigation.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"304 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115377964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Investigation of Multi-Layer Perceptron with propagation of glial pulse to two directions 神经脉冲双向传播的多层感知器研究
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6271698
C. Ikuta, Y. Uwate, Y. Nishio
{"title":"Investigation of Multi-Layer Perceptron with propagation of glial pulse to two directions","authors":"C. Ikuta, Y. Uwate, Y. Nishio","doi":"10.1109/ISCAS.2012.6271698","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271698","url":null,"abstract":"A glia is nervous cell which exists in a brain. The glia can transmit signal to other glias and neurons by change of ions' densities. We have an interest in this feature of the glia. We consider that we can apply this feature to an artificial neural network. In this study, we propose a Multi-Layer Perceptron (MLP) with propagation of glial pulse to two directions. The proposed MLP has the glias in a hidden layer. The glias are connected with neurons and are excited by the outputs of neurons. The exciting glias generate pulses and the pulses affect neurons' thresholds and neighboring glias. We consider that the MLP obtains the relationships of position of neurons in the hidden layer and this information give good influence to the MLP leaning. We confirm that the proposed MLP has better learning performance than the conventional MLP. Moreover, we confirm that the performance of the proposed MLP is changed by some conditions of propagation of the glial pulse.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115713607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
DCE3 - An universal real-time clustering engine DCE3——一个通用的实时集群引擎
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6272015
A. Wassatsch, R. Richter
{"title":"DCE3 - An universal real-time clustering engine","authors":"A. Wassatsch, R. Richter","doi":"10.1109/ISCAS.2012.6272015","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6272015","url":null,"abstract":"In this paper we describe an universal algorithm for data clustering on hardware level. By utilization of a software-inspired hardware architecture, the clustering task can be executed by a data clustering engine (DCE) in a pipelined data stream mode with a latency of only one frame. The scalable architecture of the clustering core allows a quick adaption of the engine to the specific needs of the target application. Furthermore, a prototype implementation in a TSMC 65nm low power CMOS process and an outlook on the final design for the Belle II experiment at KEK/Japan will be presented.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125226680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Live demonstration: High fill factor CIS based on single inverter architecture 现场演示:基于单逆变器架构的高填充系数CIS
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6272142
Sang-Jin Lee, O. Kavehei, K. Eshraghian, Kyoung-Rok Cho
{"title":"Live demonstration: High fill factor CIS based on single inverter architecture","authors":"Sang-Jin Lee, O. Kavehei, K. Eshraghian, Kyoung-Rok Cho","doi":"10.1109/ISCAS.2012.6272142","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6272142","url":null,"abstract":"This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDD as low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116979876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dual queue based rate selecting schedule for throughput enhancement in WLANs 基于双队列的无线局域网吞吐量选择方案
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6272086
Dongwan Kim, Wan-Seon Lim, Jongsun Park
{"title":"Dual queue based rate selecting schedule for throughput enhancement in WLANs","authors":"Dongwan Kim, Wan-Seon Lim, Jongsun Park","doi":"10.1109/ISCAS.2012.6272086","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6272086","url":null,"abstract":"In IEEE 802.11 WLANs, a fixed low transmission rate is used for multicast transmissions regardless of channel conditions of receivers. This may lead to inefficient use of wireless channel, especially when access point (AP) has both unicast and multicast data frames in the transmission queue. In this paper, we propose a dual queue based rate selecting schedule scheme for efficient use of wireless channel. In contrast to the legacy WLAN AP having a single FIFO queue, AP in the proposed scheme maintains two separate queues at the AP, one for unicast data and another for multicast data. When the AP accesses wireless channel, it decides a type of data (unicast or multicast) and transmission rate to be sent according to the channel condition and the delay boundary of multicast data. Our simulation results show that the proposed scheme increases the average data rate and energy consumption saving up to 13.7% compared to the auto rate fallback (ARF) which determines the transmission data rate only considering the channel condition.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117188052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Correlated jitter sampling for jitter cancellation in pipelined TDC 在流水线TDC中进行相关抖动采样以消除抖动
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6272164
Taehwan Oh, Hariprasath Venkatram, J. Guerber, U. Moon
{"title":"Correlated jitter sampling for jitter cancellation in pipelined TDC","authors":"Taehwan Oh, Hariprasath Venkatram, J. Guerber, U. Moon","doi":"10.1109/ISCAS.2012.6272164","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6272164","url":null,"abstract":"In this paper, the Correlated Jitter Sampling (CJS) technique, which alleviates the jitter induced error from the time reference in pipelined Time-to-Digital Converter (TDC), is proposed. The auxiliary pipelined TDC is employed to remove the jitter induced error of the main pipelined TDC in the CJS technique. A 12b pipelined TDC adopting the CJS technique in the 1st time quantization stage is simulated to validate the proposed technique. Simulation results show that the TDC can achieve a flat SNDR performance of 70dB regardless of the jitter from time reference up to 25% jitter of 1TLSB in reference clock, which is the maximum error allowed within a designed redundancy range of the pipelined TDC.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121256465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A power-efficient sizing methodology of SAR ADCs 一种SAR adc的节能尺寸方法
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6272037
Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin
{"title":"A power-efficient sizing methodology of SAR ADCs","authors":"Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang, Cheng-Wu Lin","doi":"10.1109/ISCAS.2012.6272037","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6272037","url":null,"abstract":"Analog-to-digital converter (ADC) is a vital component for modern electronic systems, but designing an ADC usually takes much time and effort. Though several synthesis methods have been presented for analog circuits, there exists limited works focusing on ADC design automation. In this paper, we propose a systematic sizing methodology to minimize the power consumption for successive approximation register (SAR) ADCs in transistor level. This method manipulates the characteristics of SAR ADC to develop an efficient searching algorithm for shortening the sizing time. The time complexity of our method is O(2 log2 |S|), where jSj is the number of candidates in the searching space. According to the proposed sizing flow, we develop a sizing tool which is independent of manufacturing process and is able to minimize power consumption for SAR ADCs. By using the developed sizing tool, a proof-of-concept prototype was carried out within only 15 minutes and fabricated in a 1P4M 0.11μm process. The measurement results show the prototype demonstrates a high competitiveness compared to other state-of-the-art works on performance and power efficiency.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127125332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Stereo matching with pixel classification and reliable disparity propagation 立体匹配与像素分类和可靠的视差传播
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6271641
Weichen Wang, S. Goto
{"title":"Stereo matching with pixel classification and reliable disparity propagation","authors":"Weichen Wang, S. Goto","doi":"10.1109/ISCAS.2012.6271641","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271641","url":null,"abstract":"In this paper, we propose a novel high-speed stereo matching algorithm using pixel classification and reliable disparity propagation. While the research on stereo matching has such a long history and many state-of-art strategies have been introduced in recent years, the contradiction between the quality and the time consumes has not yet been solved. Our stereo method tackles this problem with two key contributions. First, we classify all the pixels into two categories: consecutive pixels and isolated pixels. When we perform matching cost aggregation, different supports are constructed for different types of pixels. For a consecutive pixel, an orthogonal local support skeleton is adaptively constructed. For an isolated pixel, we build an adaptive binary window. Second, we simultaneously conduct the matching cost aggregation and reliability detection. Once a reliable disparity is found, we propagate it to the whole support region. Experiments show that this algorithm can significantly reduce the computational complexity and ensure the accuracy of the result at the same time.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127306928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Dynamic characterization of building electrical loads by equivalent energy circuit analysis 基于等效能量电路分析的建筑电负荷动态特性研究
2012 IEEE International Symposium on Circuits and Systems Pub Date : 2012-05-20 DOI: 10.1109/ISCAS.2012.6271450
Mohammed Muthalib, C. Nwankpa
{"title":"Dynamic characterization of building electrical loads by equivalent energy circuit analysis","authors":"Mohammed Muthalib, C. Nwankpa","doi":"10.1109/ISCAS.2012.6271450","DOIUrl":"https://doi.org/10.1109/ISCAS.2012.6271450","url":null,"abstract":"Enhanced metering and actuating capabilities brought about by the information embedded power system upgrade is shedding new light on load modeling. Building loads that were previously considered to be static have to be reevaluated to reflect their dynamic characteristics. This work proposes a method to evaluate the dynamic behavior of buildings by creating an equivalent energy circuit model to represent the building electrical load. The circuit model is easily integrated into power flow studies thereby transporting building dynamic load models from planning and load prediction into the field of operations.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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