Sang-Jin Lee, O. Kavehei, K. Eshraghian, Kyoung-Rok Cho
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Live demonstration: High fill factor CIS based on single inverter architecture
This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The chip operated under a +VDD as low as 500 mV with power consumption of only 27 nW per pixel. The fill factor is 58%, which is significantly larger than those conventional CMOS imagers.
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