{"title":"DCE3——一个通用的实时集群引擎","authors":"A. Wassatsch, R. Richter","doi":"10.1109/ISCAS.2012.6272015","DOIUrl":null,"url":null,"abstract":"In this paper we describe an universal algorithm for data clustering on hardware level. By utilization of a software-inspired hardware architecture, the clustering task can be executed by a data clustering engine (DCE) in a pipelined data stream mode with a latency of only one frame. The scalable architecture of the clustering core allows a quick adaption of the engine to the specific needs of the target application. Furthermore, a prototype implementation in a TSMC 65nm low power CMOS process and an outlook on the final design for the Belle II experiment at KEK/Japan will be presented.","PeriodicalId":283372,"journal":{"name":"2012 IEEE International Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"DCE3 - An universal real-time clustering engine\",\"authors\":\"A. Wassatsch, R. Richter\",\"doi\":\"10.1109/ISCAS.2012.6272015\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we describe an universal algorithm for data clustering on hardware level. By utilization of a software-inspired hardware architecture, the clustering task can be executed by a data clustering engine (DCE) in a pipelined data stream mode with a latency of only one frame. The scalable architecture of the clustering core allows a quick adaption of the engine to the specific needs of the target application. Furthermore, a prototype implementation in a TSMC 65nm low power CMOS process and an outlook on the final design for the Belle II experiment at KEK/Japan will be presented.\",\"PeriodicalId\":283372,\"journal\":{\"name\":\"2012 IEEE International Symposium on Circuits and Systems\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE International Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2012.6272015\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE International Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2012.6272015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we describe an universal algorithm for data clustering on hardware level. By utilization of a software-inspired hardware architecture, the clustering task can be executed by a data clustering engine (DCE) in a pipelined data stream mode with a latency of only one frame. The scalable architecture of the clustering core allows a quick adaption of the engine to the specific needs of the target application. Furthermore, a prototype implementation in a TSMC 65nm low power CMOS process and an outlook on the final design for the Belle II experiment at KEK/Japan will be presented.