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Sixth International Conference on Application of Concurrency to System Design (ACSD'06)最新文献

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Towards an Algebra of Abstractions for Communicating Processes 通信过程的抽象代数
Sixth International Conference on Application of Concurrency to System Design (ACSD'06) Pub Date : 2006-06-28 DOI: 10.1109/ACSD.2006.34
M. Koutny, G. Pappalardo, Marta Pietkiewicz-Koutny
{"title":"Towards an Algebra of Abstractions for Communicating Processes","authors":"M. Koutny, G. Pappalardo, Marta Pietkiewicz-Koutny","doi":"10.1109/ACSD.2006.34","DOIUrl":"https://doi.org/10.1109/ACSD.2006.34","url":null,"abstract":"It is often desirable to describe the interface of an implementation system at a different (usually more detailed) level of abstraction to the interface of the relevant specification. This calls for a relation aimed at formalising the notion that a process is an acceptable implementation of another target process in the event that they possess different interfaces. This paper formulates a suitable implementation relation between the observable behaviours of the implementation and the target process using CSP. Interface difference and bridging is modelled by endowing the implementation relation with parameters, called extraction patterns, instrumental to interpreting implementation behaviour as target behaviour. Reasonable notions of implementation and extraction patterns should result in a relation satisfying the realisability and compositionality properties. The former means that, if target and implementation in fact have the same interface, then the implementation relation between them collapses into the standard implementation pre-order of CSP. Compositionality allows a target composed of several connected systems to be implemented by connecting their respective implementations. With respect to previous work, the paper drops a restriction that prevented broadcast and other group communication to be modelled, and admits fully general specification processes. The novelty of the approach presented here is that it introduces operations over extraction patterns, mimicking (and being compatible with) operations on processes","PeriodicalId":282333,"journal":{"name":"Sixth International Conference on Application of Concurrency to System Design (ACSD'06)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123850359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simulation and Verification of Asynchronous Systems by means of a Synchronous Model 异步系统的同步模型仿真与验证
Sixth International Conference on Application of Concurrency to System Design (ACSD'06) Pub Date : 2006-06-28 DOI: 10.1109/ACSD.2006.24
N. Halbwachs, Louis Mandel
{"title":"Simulation and Verification of Asynchronous Systems by means of a Synchronous Model","authors":"N. Halbwachs, Louis Mandel","doi":"10.1109/ACSD.2006.24","DOIUrl":"https://doi.org/10.1109/ACSD.2006.24","url":null,"abstract":"Synchrony and asynchrony are commonly opposed to each other. Now, in embedded applications, actual solutions are often situated in between, with synchronous processes composed in a partially asynchronous way. Examples of such intermediate solutions are GALS, quasi-synchronous periodic processes, deadline-driven task scheduling. In this paper, we illustrate the use of the synchronous paradigm to model and validate such partially asynchronous applications. We show that, through the use of sporadic activation of processes and simulation of non-determinism by the way of auxiliary inputs, the synchronous paradigm allows a precise control of asynchrony. The approach is illustrated on a real case study, proposed in the framework of the European integrated project \"Assert\"","PeriodicalId":282333,"journal":{"name":"Sixth International Conference on Application of Concurrency to System Design (ACSD'06)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
High-level Synthesis for Highly Concurrent Hardware Systems 高并发硬件系统的高级综合
Sixth International Conference on Application of Concurrency to System Design (ACSD'06) Pub Date : 2006-06-28 DOI: 10.1109/ACSD.2006.9
Sunan Tugsinavisut, R. Su, P. Beerel
{"title":"High-level Synthesis for Highly Concurrent Hardware Systems","authors":"Sunan Tugsinavisut, R. Su, P. Beerel","doi":"10.1109/ACSD.2006.9","DOIUrl":"https://doi.org/10.1109/ACSD.2006.9","url":null,"abstract":"This paper presents new approaches for high-level synthesis of highly concurrent hardware systems modeled with timed marked graphs. Unlike control data flow graphs (CDFGs) used in most high-level synthesis works, timed marked graphs can easily express highly concurrent hardware systems, including those with pipelined and multithreading behaviors. We first propose both exact and heuristic scheduling and allocation algorithms without considering binding. These algorithms, however, do not allow the cost associated with binding to be included. Thus, we propose concurrent scheduling and binding algorithms that include control complexity. Lastly, we describe and compare experimental results on a variety of digital signal processing (DSP) applications","PeriodicalId":282333,"journal":{"name":"Sixth International Conference on Application of Concurrency to System Design (ACSD'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129888943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Modelling and verification of authentication using enhanced net semantics of SPL (Security Protocol Language) 使用SPL(安全协议语言)增强网络语义的身份验证建模和验证
Sixth International Conference on Application of Concurrency to System Design (ACSD'06) Pub Date : 2006-06-28 DOI: 10.1109/ACSD.2006.12
Roland Bouroulet, Hanna Klaudel, E. Pelz
{"title":"Modelling and verification of authentication using enhanced net semantics of SPL (Security Protocol Language)","authors":"Roland Bouroulet, Hanna Klaudel, E. Pelz","doi":"10.1109/ACSD.2006.12","DOIUrl":"https://doi.org/10.1109/ACSD.2006.12","url":null,"abstract":"This paper proposes an enhanced translation of Security Protocol Language (SPL) in high-level Petri nets in order to allow to prove automatically, using model-checking techniques, the authentication property of Needham-Schroeder-Lowe (NSL) protocol. The proposed approach generates finite nets and goes this way beyond the limitation which was imposed by the previous semantics due to the treatment of the replication operator. In order to reach this goal, we modify the way attacks are modelled. Due to fact that the presented approach focuses on the treatment of the protocol environment, it may be successfully reused for automated verification of properties of other security protocols","PeriodicalId":282333,"journal":{"name":"Sixth International Conference on Application of Concurrency to System Design (ACSD'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131257336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On process-algebraic verification of asynchronous circuits 异步电路的过程代数验证
Sixth International Conference on Application of Concurrency to System Design (ACSD'06) Pub Date : 2006-06-28 DOI: 10.1109/ACSD.2006.16
Xu Wang, M. Kwiatkowska
{"title":"On process-algebraic verification of asynchronous circuits","authors":"Xu Wang, M. Kwiatkowska","doi":"10.1109/ACSD.2006.16","DOIUrl":"https://doi.org/10.1109/ACSD.2006.16","url":null,"abstract":"This paper develops a theoretical basis for using process algebra and associated model checking tools to verify asynchronous circuits. We extend existing verification theory for asynchronous circuits, and integrate it into the framework of standard process algebra theory. Our theory permits analysis of safeness (i.e. choke) and progress (i.e. illegal stop, divergence and relative starvation) conditions. We show how the model can be translated into CSP, and how the satisfaction of safeness and progress requirements can be reduced to refinement checks in CSP","PeriodicalId":282333,"journal":{"name":"Sixth International Conference on Application of Concurrency to System Design (ACSD'06)","volume":"125 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120841454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Verification of a Data Synchronization Circuit For All Time 一个数据同步电路的验证
Sixth International Conference on Application of Concurrency to System Design (ACSD'06) Pub Date : 2006-06-28 DOI: 10.1109/ACSD.2006.35
Geoffrey M. Brown
{"title":"Verification of a Data Synchronization Circuit For All Time","authors":"Geoffrey M. Brown","doi":"10.1109/ACSD.2006.35","DOIUrl":"https://doi.org/10.1109/ACSD.2006.35","url":null,"abstract":"This paper presents a model and automated proof for a synchronizer circuit that is commonly used to reliably transfer data across clock domains. In contrast with previous work, this paper describes a proof that is valid for all clock rates and phases meeting modest constraints. Furthermore, the proof was realized with an existing model checker - SAL","PeriodicalId":282333,"journal":{"name":"Sixth International Conference on Application of Concurrency to System Design (ACSD'06)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129611704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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