一个数据同步电路的验证

Sixth International Conference on Application of Concurrency to System Design (ACSD'06) Pub Date : 2006-06-28 DOI:10.1109/ACSD.2006.35

Geoffrey M. Brown

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引用次数: 5

摘要

本文提出了一种同步器电路的模型和自动证明，这种同步器电路通常用于跨时钟域可靠地传输数据。与以往的工作相比，本文描述了一个对满足适度约束的所有时钟速率和相位有效的证明。在此基础上，利用已有的模型检查器SAL实现了验证

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Verification of a Data Synchronization Circuit For All Time

This paper presents a model and automated proof for a synchronizer circuit that is commonly used to reliably transfer data across clock domains. In contrast with previous work, this paper describes a proof that is valid for all clock rates and phases meeting modest constraints. Furthermore, the proof was realized with an existing model checker - SAL

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Sixth International Conference on Application of Concurrency to System Design (ACSD'06)

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