2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)最新文献

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SPARTA-COTS: A Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits SPARTA-COTS:一种用于COTS集成电路中顺序木马检测的激光探测方法
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337728
Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujjwal Guin, Farimah Farahmandi, M. Tehranipoor
{"title":"SPARTA-COTS: A Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits","authors":"Andrew Stern, Dhwani Mehta, Shahin Tajik, Ujjwal Guin, Farimah Farahmandi, M. Tehranipoor","doi":"10.1109/PAINE49178.2020.9337728","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337728","url":null,"abstract":"Rapid advancements in integrated circuit (IC) technology have been led by the private sector. This leadership has resulted in a widespread dependence of commercial-off-the-shelf (COTS) components in our electronic systems. However, being dependent upon potentially compromised hardware serves as a threat to our security. Hardware Trojans, which can extract sensitive information and disrupt system operations, can be inserted into COTS ICs by untrusted design and fabrication facilities. Checking for the existence of Trojans using conventional methods requires a complex test process and design-level modifications, which requires trusted design information, making them unsuitable for COTS components. On the other hand, for a high confidence detection of Trojans, an exhaustive inspection may be required using destructive reverse-engineering techniques. However, such methods are quite expensive, not applicable to all chips due to their destructive nature, and very time-consuming. In this work, we propose SPARTA-COTS, a non-destructive laser probing approach for Trojan detection in COTS ICs, which detects sequential hardware Trojans by leveraging existing scan chain architecture. SPARTA can differentiate between benign scan flip-flops and malicious sequential hardware Trojans by creating a 2-dimensional frequency activity map of the backside silicon at the clock and scan input frequencies using electrooptical frequency mapping (EOFM). Consequently, SPARTA is capable of confidently identifying Trojan flip-flops using image processing techniques. To validate our claims, we present automated detection results on a 28 nm device.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132985316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Automated Detection and Localization of Counterfeit Chip Defects by Texture Analysis in Infrared (IR) Domain 基于红外纹理分析的伪造芯片缺陷自动检测与定位
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337739
P. Ghosh, Ulbert J. Botero, F. Ganji, D. Woodard, R. Chakraborty, Domenic Forte
{"title":"Automated Detection and Localization of Counterfeit Chip Defects by Texture Analysis in Infrared (IR) Domain","authors":"P. Ghosh, Ulbert J. Botero, F. Ganji, D. Woodard, R. Chakraborty, Domenic Forte","doi":"10.1109/PAINE49178.2020.9337739","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337739","url":null,"abstract":"Today's globalized supply chain for electronics design, fabrication, and distribution has resulted in a proliferation of counterfeit chips. Recycled and remarked chips are the most common counterfeit types in the market, and prior work has shown that physical inspection is the best approach to detect them. However, it can be time-consuming, expensive, and destructive while relying on the use of subject matter experts. This paper proposes a low-cost, automated detection technique that examines surface variations within and between chips to identify defective chips. Further, it can estimate the location of the defects for additional analysis. The proposed method only requires a cheap IR camera-based setup to capture images of the chip package surface and is completely unsupervised and non-destructive. Experimental results on 25 chips in our lab demonstrate 100% detection accuracy.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116706209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Tracking Cloned Electronic Components using a Consortium-based Blockchain Infrastructure 使用基于联盟的区块链基础设施跟踪克隆电子元件
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337735
Jason Vosatka, Andrew Stern, M.M. Hossain, Fahim Rahman, Jeffery Allen, M. Allen, Farimah Farahmandi, M. Tehranipoor
{"title":"Tracking Cloned Electronic Components using a Consortium-based Blockchain Infrastructure","authors":"Jason Vosatka, Andrew Stern, M.M. Hossain, Fahim Rahman, Jeffery Allen, M. Allen, Farimah Farahmandi, M. Tehranipoor","doi":"10.1109/PAINE49178.2020.9337735","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337735","url":null,"abstract":"The globalized electronics supply chain relies on many untrusted entities to move components across the world. This, in turn, increases the threat of counterfeit integrated circuits (ICs) being inserted into the supply chain then installed into mission critical systems. A number of methods for detecting counterfeit ICs exist; however, applications of models to rapidly and non-destructively detect cloned ICs are lacking. Moreover, no trustworthy data storage and verification mechanism exists in the current supply chain that can provide identification and tracking of authentic and cloned ICs. In this work, we propose a novel framework to address these detection and tracking problems at each stage of the electronics supply chain. We leverage a consortium-style blockchain infrastructure to offer tamper-proof data enrollment and verification. We propose the algorithm and model for confidently identifying authentic and cloned ICs, and offer next stage tracking by verifying general and restricted datasets in the blockchain. The experimental result demonstrates how entities can verify and track the cloned chips with a given level of confidence in the presence of noise.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"315 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123681067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sample Mounting Methods for Precision Delayering of 130 nm Integrated Circuit Devices 130纳米集成电路器件精密分层的样品安装方法
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337731
Jonathan Scholl, Y. Patel, Joshua Baur, Adam G. Kimura, Adam R. Waite, J. Kelley, G. Via
{"title":"Sample Mounting Methods for Precision Delayering of 130 nm Integrated Circuit Devices","authors":"Jonathan Scholl, Y. Patel, Joshua Baur, Adam G. Kimura, Adam R. Waite, J. Kelley, G. Via","doi":"10.1109/PAINE49178.2020.9337731","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337731","url":null,"abstract":"This paper reviews different methods for mounting and integrated circuit (IC) for delayering. In this work, several 130nm technology devices are observed during the delayering process as a means of evaluating the advantages and disadvantages of various mounting techniques. Suitability for chemical mechanical polishing, wet etching, and dry etching is considered.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132238596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
[Front matter] (前页)
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/paine49178.2020.9337732
{"title":"[Front matter]","authors":"","doi":"10.1109/paine49178.2020.9337732","DOIUrl":"https://doi.org/10.1109/paine49178.2020.9337732","url":null,"abstract":"","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129393330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ReCon: From the Bitstream to Piracy Detection 侦察:从比特流到盗版检测
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337563
Grant Skipper, Christopher Sozio, Adam Duncan, Andrew Lukefahr, M. Swany
{"title":"ReCon: From the Bitstream to Piracy Detection","authors":"Grant Skipper, Christopher Sozio, Adam Duncan, Andrew Lukefahr, M. Swany","doi":"10.1109/PAINE49178.2020.9337563","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337563","url":null,"abstract":"Field-Programmable Gate Arrays (FPGAs) are used almost everywhere, from smart-phones to datacenters. FPGA functionality is determined by the intellectual property (IP) encoded within a vendor-proprietary binary configuration file, or bitstream, that is deployed on these devices. The potential value offered by IP creates many incentives for an adversary to attempt to steal it. The opaque nature of vendor bitstream formats has thus far limited the ability to detect stolen IP in deployed FPGAs. In this work we demonstrate the ability to detect instances of IP piracy given ONLY the FPGA configuration bitstream and a golden user netlist. While prior works have shown it is possible to reverse-engineer FPGA bitstreams into an underlying structural netlist, in isolation this netlist is of limited utility. We take this a step further by introducing ReCon, a tool to automatically assist in detecting pirated IP within a bitstream. ReCon first extracts a netlist from an unknown bitstream, then applies subgraph isomorphism algorithms to detect IP within the extracted netlist that are pirated from an original, or user, IP. Our experiments demonstrate ReCon as an effective method for piracy detection because it allows for a composite comparison between two bitstreams without needing to manually reverse engineer circuits and identify submodules.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133524638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
SHADE: Automated Refinement of PCB Component Estimates Using Detected Shadows SHADE:使用检测到的阴影自动改进PCB组件估计
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337564
Nathan Jessurun, Olivia P. Paradis, M. Tehranipoor, N. Asadizanjani
{"title":"SHADE: Automated Refinement of PCB Component Estimates Using Detected Shadows","authors":"Nathan Jessurun, Olivia P. Paradis, M. Tehranipoor, N. Asadizanjani","doi":"10.1109/PAINE49178.2020.9337564","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337564","url":null,"abstract":"Automated Visual Inspection (AVI) is an established approach for Printed Circuit Board (PCB) analysis. Several existing AVI methods have been well-developed for quality assurance, but not for hardware security and trust assessment. The main distinction between these two cases is that a golden sample (reference PCB) is available in the former application but is not guaranteed in the latter. Hence, conventional AVI approaches falsely detect many non-components (e.g. traces, vias, board text) as legitimate ones (e.g. resistors, capacitors, transistors). Such false detections cripple the scalability of hardware assurance approaches. In this paper, we propose an algorithm which exploits shadows cast by surface-mount components to accurately distinguish them from their invalid counterparts. It refines an initial component detection estimate by ruling out false positives. Moreover, the algorithm yields a per-component confidence metric which adds flexibility to the process' sensitivity threshold. Tests on a sample PCB indicate as many as half of the initial false positives from a component estimate can be removed while retaining 96% of the true positives.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115582100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Using Digital Sensors to Leverage Chips' Security 利用数字传感器提高芯片安全性
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337730
Mohammad Ebrahimabadi, Md Toufiq Hasan Anik, J. Danger, S. Guilley, Naghmeh Karimi
{"title":"Using Digital Sensors to Leverage Chips' Security","authors":"Mohammad Ebrahimabadi, Md Toufiq Hasan Anik, J. Danger, S. Guilley, Naghmeh Karimi","doi":"10.1109/PAINE49178.2020.9337730","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337730","url":null,"abstract":"One way for an attacker to break a system is to perturb it. Expected effects are countermeasure deactivation or data corruption to disclose sensitive information. The prevention of such actions relies on detection of abnormal operating conditions. Digital sensors can play this role. A digital sensor is built out of the very same standard cells as the user logic to be protected. This ensures the advantage that the sensor and the user logic are exposed to the same stress. Balancing True positives and False negatives is a tough question in field of sensors. This is a general issue, and the best way to mitigate this paradox is to thoroughly investigate their properties, through simulations and real experiments. This results in characterizations, which in turn allows for intuitions on how to handle sensing values. In this paper, we exhibit the complex relationships between propagation times in logic and environmental conditions. Those results reinforce the relevance of the digital sensor versus the adversarial manipulation of environmental conditions: fewer false alarms are raised even if temperature (resp. voltage) is extreme, provided the effect is balanced by voltage (resp. temperature). Owing to the complex relationship between propagation delays, temperature and voltage, this cannot happen with a set of independent temperature and voltage sensors.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130664153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
New physical analysis capability for counterfeit electronics and reverse engineering 新的物理分析能力,假冒电子产品和逆向工程
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337737
Greg M. Johnson, C. Hartfield, S. Mueller, M. Kaestner
{"title":"New physical analysis capability for counterfeit electronics and reverse engineering","authors":"Greg M. Johnson, C. Hartfield, S. Mueller, M. Kaestner","doi":"10.1109/PAINE49178.2020.9337737","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337737","url":null,"abstract":"a new cross-section workflow for improved access to buried structures within electronic devices has been developed. A focused-ion beam scanning-electron microscope (FIB-SEM) system has been integrated by attaching a femtosecond laser to the loadlock chamber, enabling rapid site-specific preparation of internal device details. Evidence is provided that compared with traditional techniques, this new workflow enabled by the Crossbeam laser FIB-SEM offers improved speed and productivity, while simultaneously delivering more precise dimensional sampling and reduced damage to the surrounding area.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Techniques to Thwart Surreptitiously Altered PCBs 阻止秘密改变pcb的技术
2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337567
S. Russ
{"title":"Techniques to Thwart Surreptitiously Altered PCBs","authors":"S. Russ","doi":"10.1109/PAINE49178.2020.9337567","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337567","url":null,"abstract":"Printed circuit boards (PCBs, also known as Printed Wiring Boards or PWBs) are in nearly ubiquitous use in electronic and computer systems. While often regarded as mundane, PCBs provide vital interconnection capabilities. Incorrect PCB design causes systems to fail. Cybersecurity efforts have been justifiably focused on integrated circuits due to the possibility of malicious alteration, but little or no attention has been paid to the PCB. Conversely, malicious alteration of PCBs is extremely simple. After reviewing work on the ways that PCBs can be altered, this presents a taxonomy of circuit-board attacks and techniques for detecting alterations.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126988856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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