2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)最新文献_第2页

Compromising device security via NVM controller vulnerability 通过NVM控制器漏洞危及设备安全

2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337736

S. Skorobogatov

引用次数: 1

Toward an RF side-channel reverse engineering tool 一个射频侧信道逆向工程工具

2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337729

Miller Wilt, Megan M. Baker, S. Papadakis

{"title":"Toward an RF side-channel reverse engineering tool","authors":"Miller Wilt, Megan M. Baker, S. Papadakis","doi":"10.1109/PAINE49178.2020.9337729","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337729","url":null,"abstract":"Digital technology advances quickly. New versions of both processors and software are released on a timescale of months, and each modification brings the potential for new security threats. We investigate here the use of RF side channel collection and a machine learning-based classifier for a general-purpose reverse-engineering tool. Ideally, such a tool would enable a user to learn as much as possible about the device under test (DUT) with minimal interaction with that DUT. Furthermore, to enable rapid updates, training of the tool to classify new hardware and software should not require detailed knowledge of the new DUT. We demonstrate identification of various processes running on an Intel Atom single-core processor using RF side channel analysis and machine learning. One classifier was able to distinguish among BIOS, Windows 10, and Ubuntu Linux, and another among Ubuntu Linux 16.04, 18.04, and 20.04. A classifier was built that can detect processes running in the background on Windows or Linux, including a web browser and word processor on each. Finally, a classifier was built that detects the WannaCry ransomware operating. For all of these capabilities, for both training and testing, collection of RF leakage was done with minimal interaction with the DUT; the DUT was booted and the probe was placed by hand near the CPU to collect the RF side-channel leakage asynchronously and without a trigger. Performance was above 99.9% with a fixed probe position, and above 99% for probe that was placed for each measurement. We describe the application of 1D deep convolutional neural networks inspired by natural language processing algorithms to the RF data, and how very high performance classification of even very subtle RF signatures can be achieved.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133035380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Benefits and Challenges of Utilizing Hardware Performance Counters for COPPA Violation Detection 利用硬件性能计数器进行COPPA违规检测的好处和挑战

2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337566

Abraham Peedikayil Kuruvila, Ayush Arunachalam, K. Basu

{"title":"Benefits and Challenges of Utilizing Hardware Performance Counters for COPPA Violation Detection","authors":"Abraham Peedikayil Kuruvila, Ayush Arunachalam, K. Basu","doi":"10.1109/PAINE49178.2020.9337566","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337566","url":null,"abstract":"This paper analyzes the findings of [1] regarding user privacy in Android apps. Mobile applications have come under scrutiny for allegations of data breaches and leaks, such as usernames, email IDs, and locations. Subsequent documented instances of these violations have led to the Federal Trade Commission (FTC) imposing severe penalties on the app developers. Recently, apps such as TikTok and BabyBus were sanctioned and fined for flouting privacy regulations. To ensure the safety of young users, the Children's Online Privacy Protection Act (COPPA) was enacted to monitor the data usage of apps dedicated to children. Hence, it is imperative that children's apps adhere to COPPA. Towards this end, [1] proposes COPPA Tracking by Checking Hardware-level Activity (COPPTCHA), a Hardware Performance Counter-based (HPC) approach to validate COPPA-compliance of Android apps. The HPC data is used to train a Machine Learning classifier, which predicts COPPA violations with 99% accuracy. This paper summarizes the benefits and pitfalls of using HPCs for detecting COPPA violations.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115404257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

From Silicon to Simulation: A Full Decomposition of a Fabricated 130 nm Serial Peripheral Interface for Establishing an Assurance Baseline Root-of-Trust 从硅到仿真:用于建立保证基线信任根的制造130 nm串行外设接口的完全分解

2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337733

Adam G. Kimura, Adam R. Waite, Jonathan Scholl, James Schaffranek, Matt Sutter, G. Via

{"title":"From Silicon to Simulation: A Full Decomposition of a Fabricated 130 nm Serial Peripheral Interface for Establishing an Assurance Baseline Root-of-Trust","authors":"Adam G. Kimura, Adam R. Waite, Jonathan Scholl, James Schaffranek, Matt Sutter, G. Via","doi":"10.1109/PAINE49178.2020.9337733","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337733","url":null,"abstract":"This paper reviews the decomposition of a fabricated Serial Peripheral Interface (SPI) that was manufactured in a 130 nm process node technology to establish a verification and validation methodology for baselining microelectronics assurance. The fabricated SPI goes through a delayering process where each target layer is captured and imaged using a Raith 150 Chipscanner. The features for each layer are extracted allowing a GDSII layout file to be generated and subsequent design netlist to be recovered. The extracted GDSII was compared to the original reference GDSII, exposing additional fill cells that were added to the design at the foundry. The recovered netlist was validated as logically equivalent to the original golden design netlist and was simulated in the original verification testbench, passing 100% of the original model checks. By passing the GDSII comparison, functional model checks, and logical equivalence checks, the fabricated SPI was determined to be trusted. A methodology for establishing an assurance baseline root-of-trust has been proven.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133641254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Semi-Supervised Automated Layer Identification of X-ray Tomography Imaged PCBs x射线断层成像pcb的半监督自动层识别

2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337738

Ulbert J. Botero, F. Ganji, N. Asadizanjani, D. Woodard, Domenic Forte

{"title":"Semi-Supervised Automated Layer Identification of X-ray Tomography Imaged PCBs","authors":"Ulbert J. Botero, F. Ganji, N. Asadizanjani, D. Woodard, Domenic Forte","doi":"10.1109/PAINE49178.2020.9337738","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337738","url":null,"abstract":"Reverse engineering (RE) for printed circuit boards (PCB) can be achieved through X-ray Computed Tomography (CT) in a non-destructively yet predominantly manual process. For practical RE to be possible in applications such as obsolescence replacement and hardware assurance, it is important that this process be as automated and fast as possible. This paper introduces a framework to identify which slices of an X-ray CT 3-D PCB stack belong to what layer on a physical PCB in an automated and generalizable fashion for any X-rayed PCB. To the best of our knowledge, this is the first method for identifying the correspondence between an X-ray CT slice and layers of a PCB using reference design information, demonstrated on a 6 layered PCB. First, a spatial pyramid bag-of-visual-words technique is leveraged to enable a semi-supervised approach where the user has either digital or X-ray layout information available for heterogeneous image comparison between X-ray CT image slices. Second, a weighting scheme based on entropy of an image region is proposed. Our results show near perfect quantitative and qualitative layer identification. The completion of this step facilitates improved performance in later RE stages, such as feature extraction or analysis of an X-rayed PCB.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114651257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Electronic component solderability assessment algorithm by deep external visual inspection 基于深度外部视觉检测的电子元件可焊性评估算法

2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-12-15 DOI: 10.1109/PAINE49178.2020.9337565

Eyal Weiss

{"title":"Electronic component solderability assessment algorithm by deep external visual inspection","authors":"Eyal Weiss","doi":"10.1109/PAINE49178.2020.9337565","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337565","url":null,"abstract":"Electronic component solderability is an essential capability in electronics manufacturing. It determines an electronic component's ability to be reliably and repeatably soldered onto a circuit board in an automated production scheme. However, conventional solderability assessment is a destructive test that is performed on samples only. A novel, automatic, and non-destructive method for assessing the solderability of electronic leads based on deep visual inspection (DVI) is presented. The solderability is correlated to the surface reflectance which is degrading by corrosion and intermetallic reactions. The inspected components' solderability is assessed by acquiring micro-features in images through a combined supervised and unsupervised machine learning system. The former is designed to evaluate the homogeneity of the leads and the latter is designed for assessing soldering leads by classifying them into leads with good and poor solderability, based on their apparent-age. The models are trained using multiple images of a variety of soldering leads from different ages and therefore different solderability conditions. The experimental results show that components from the same package do not have homogenous solderability. Furthermore, while the leads mostly fit their apparent-age, some have solderability corresponding to apparent-older components. This method allows for continuous real-time 100% component screening, with very high classification accuracy. The presented method paves the way for a radical improvement in manufacturing quality by assuring that only components with good solderability are used during assembly.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133168465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

ATPG-Guided Fault Injection Attacks on Logic Locking atpg引导的逻辑锁定故障注入攻击

2020 IEEE Physical Assurance and Inspection of Electronics (PAINE) Pub Date : 2020-07-20 DOI: 10.1109/PAINE49178.2020.9337734

Ayush Jain, Tanjidur Rahman, Ujjwal Guin

{"title":"ATPG-Guided Fault Injection Attacks on Logic Locking","authors":"Ayush Jain, Tanjidur Rahman, Ujjwal Guin","doi":"10.1109/PAINE49178.2020.9337734","DOIUrl":"https://doi.org/10.1109/PAINE49178.2020.9337734","url":null,"abstract":"Logic Locking is a well-accepted protection technique to enable trust in the outsourced design and fabrication processes of integrated circuits (ICs) where the original design is modified by incorporating additional key gates in the netlist, resulting in a key-dependent functional circuit. The original functionality of the chip is recovered once it is programmed with the secret key, otherwise, it produces incorrect results for some input patterns. Over the past decade, different attacks have been proposed to break logic locking, simultaneously motivating researchers to develop more secure countermeasures. In this paper, we propose a novel stuck-at fault-based differential fault analysis (DFA) attack, which can be used to break logic locking that relies on a stored secret key. This proposed attack is based on self-referencing, where the secret key is determined by injecting faults in the key lines and comparing the response with its fault-free counterpart. A commercial ATPG tool can be used to generate test patterns that detect these faults, which will be used in DFA to determine the secret key. One test pattern is sufficient to determine one key bit, which results in at most $vertpmb{K}vert$ test patterns to determine the entire secret key of size $vertpmb{K}vert$. The proposed attack is generic and can be extended to break any logic locked circuits.","PeriodicalId":280967,"journal":{"name":"2020 IEEE Physical Assurance and Inspection of Electronics (PAINE)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133245336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13