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2016 International SoC Design Conference (ISOCC)最新文献

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A study on river water level monitoring method in a debris barrier 碎石屏障中河流水位监测方法研究
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799875
Hyo Sub Choi, Deepak Ghimire
{"title":"A study on river water level monitoring method in a debris barrier","authors":"Hyo Sub Choi, Deepak Ghimire","doi":"10.1109/ISOCC.2016.7799875","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799875","url":null,"abstract":"In this paper, the river water level monitoring method in a debris barrier is presented. There are four steps in this proposed solution: Frame difference, Thresholding & Noise refinement, Candidate point detection, and Classification. The proposed method is able to calculate water flow occupancy value and monitor the change in water flow in a dam. This technique is very efficient to give warning in case of there is any abrupt change in water flow in the river.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124034045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design-time energy optimization for asymmetric multiprocessor system-on-chip 非对称多处理器片上系统的设计时能量优化
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799828
Yonghee Yun, Young Hwan Kim
{"title":"Design-time energy optimization for asymmetric multiprocessor system-on-chip","authors":"Yonghee Yun, Young Hwan Kim","doi":"10.1109/ISOCC.2016.7799828","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799828","url":null,"abstract":"This paper proposes a static task mapping algorithm for energy-efficient embedded system design. The proposed algorithm is based on a genetic algorithm, which generates a set of solution candidates and evolves the candidates using genetic operations. During the evolvement, the proposed approach evaluates the time slack of each candidate, and then updates the candidates using a novel adaptive generation method. Experimental results show that the proposed method reduced the energy consumption by up to 16.1% and 34.1% compared to the existing methods and outperformed them in most cases.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121404012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A passband lock loop circuit system for band pass filter 一种用于带通滤波器的通带锁环电路系统
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799710
Hung-Wen Lin, Jin-Yi Lin
{"title":"A passband lock loop circuit system for band pass filter","authors":"Hung-Wen Lin, Jin-Yi Lin","doi":"10.1109/ISOCC.2016.7799710","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799710","url":null,"abstract":"This paper proposes a passband lock loop for tunable band-pass-filter (BPF). AC-coupling, swing amplification, peak conversion and low-noise S/H circuit are designed to differentiate several hundred uV of swing difference. All-digital peak-tracking-controller and FSM are also realized for easy verification and low area. The proposed loop was integrated with a BPF cell with 7-bits controls and 30M~50MHz of tuning range. In 0.18um technology, the proposed loop and BPF cell respectively occupied active area of 0.0046mm2 and 0.027mm2, and consume currents of 0.51mA and 1.44mA. With a 625kHz reference clock, the maximum period for passband tracking is 192 clock cycles.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128755162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip 片上网络中高速开关控制和调度中开关仲裁器的功率和面积标定
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799765
Sangeeta Singh, J. Ravindra, B. Naik
{"title":"Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip","authors":"Sangeeta Singh, J. Ravindra, B. Naik","doi":"10.1109/ISOCC.2016.7799765","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799765","url":null,"abstract":"Network-on-chip (NoC) is being considered as a promising model to overcome the communication bottleneck of future multicore systems. It plays an important role in determining the area and power of the entire chip. As a basic component in on-chip router, arbiter has a large impact on the performance of router. A centralized arbiter called switch arbiter resolves conflicts between the input ports to get the access for the same output port. The design of such power and area efficient switch arbiter for Network on Chip is a major challenge in DSM technology. This paper proposes a novel switch arbiter that reduces power dissipation and consumes less area in comparison to conventional switch arbiter. The novel switch arbiter has been designed using twisted ring counter instead of ring counter to increase its performance. Simulation results have been carried out using Cadence Design Framework with 180nm technology.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114270105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Full system verification of compatible microprocessors with a dual physical core verification platform 兼容微处理器的全系统验证与双物理核心验证平台
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799825
Jyun-Yan Li, Ing-Jer Huang
{"title":"Full system verification of compatible microprocessors with a dual physical core verification platform","authors":"Jyun-Yan Li, Ing-Jer Huang","doi":"10.1109/ISOCC.2016.7799825","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799825","url":null,"abstract":"This paper presents a dual physical core verification (DPCV) platform that verifies the device under verification (DUV) microprocessor with an existing compatible one at run time. Working as fault tolerance, both cores execute the same program and compare each data transaction. The DPCV synchronizes both microprocessors when data write or external interrupt occurs for data consistency and buffers the I/O data read for the DUV. If the data transactions are inconsistent, the DPCV suspends both cores after the fault for verification.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116095619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A lightweight metric for the evaluation of network congestion in NoC-based MPSoC 基于noc的MPSoC中网络拥塞评估的轻量级度量
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799859
Yang Huang, Letian Huang, Xiaohang Wang
{"title":"A lightweight metric for the evaluation of network congestion in NoC-based MPSoC","authors":"Yang Huang, Letian Huang, Xiaohang Wang","doi":"10.1109/ISOCC.2016.7799859","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799859","url":null,"abstract":"An effective run-time application mapping algorithm needs to reduce network congestion due to its significant impact on network performance. In this paper, we propose a lightweight congestion evaluation metric for application mapping algorithms in NoC-based MPSoC. We obtain information from task graphs and the mapping results, and use it to calculate a congestion metric to evaluate the link interference for a given communication flow. The congestion metric is the number of flows which share the same link with the given flow, it reflects both internal and external congestion. The congestion metric is accurate and lightweight, it can be used in runtime application mapping algorithms and other real-time tasks. Simulation result shows a strong correlation between the metric value and the average latency. Compared with other similar metrics, our congestion metric shows much greater accuracy.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126208872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA) 用于非易失性现场可编程门阵列(FPGA)的自旋扭矩传递磁性RAM的容差和低功耗查找表(LUT)
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799753
Kangwook Jo, Kyungseon Cho, H. Yoon
{"title":"Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA)","authors":"Kangwook Jo, Kyungseon Cho, H. Yoon","doi":"10.1109/ISOCC.2016.7799753","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799753","url":null,"abstract":"The non-volatile field programmable gate array (FPGA) is a promising candidate for the ultra-low-power computing due to its flexibility. However, the non-volatile devices have a critical drawback of reliability due to the process variations in read operation. We propose a novel look-up table scheme using the spin-torque transfer magnetic RAM with high variation tolerance and low power consumption. The proposed 8-input look-up table (LUT) has a 74.4% smaller read power consumption than that of the conventional 8-input SRAM-based LUT. The area of the proposed LUT is comparable to that of the conventional SRAM-based LUT.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128141936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Equalization scheme analysis for high-density spin transfer torque random access memory 高密度自旋传递扭矩随机存取存储器均衡方案分析
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799752
Beomsang Yoo, T. Na, Byungkyu Song, Seong-ook Jung, Jung Pill Kim, Seung H. Kang
{"title":"Equalization scheme analysis for high-density spin transfer torque random access memory","authors":"Beomsang Yoo, T. Na, Byungkyu Song, Seong-ook Jung, Jung Pill Kim, Seung H. Kang","doi":"10.1109/ISOCC.2016.7799752","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799752","url":null,"abstract":"As the memory density increases for the big-data processing, the sensing speed is degraded because of the increased parasitic capacitive load. Thus, the equalization (EQ) scheme that is capable of improving the sensing speed has now become essential. This paper examines the effectiveness of EQ scheme on the sensing speed of offset-canceling dual-stage sensing circuit (OCDS-SC) in terms of cells per bit line (CpBL). The simulation results show that the OCDS-SC with EQ scheme achieves 3 times faster sensing time than that without EQ scheme in case of CpBL of 128. Additionally, the EQ scheme becomes more effective for reducing the sensing time according to the increase in the number of CpBL.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127025278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LNA topologies for RX carrier aggregation RX载波聚合的LNA拓扑
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799698
Jusung Kim, K. Ryu, Sungchan Kim, Sanghun Lee
{"title":"LNA topologies for RX carrier aggregation","authors":"Jusung Kim, K. Ryu, Sungchan Kim, Sanghun Lee","doi":"10.1109/ISOCC.2016.7799698","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799698","url":null,"abstract":"Performance of the low-noise amplifier (LNA) determines the sensitivity, impedance matching (reflection), and other critical parameters of the receiver. Carrier aggregation (CA) in LTE-Advanced and upcoming 5G requires the LNA to support multiple-outputs without degrading its dynamic range (DR) performance and thus requires the architectural changes. In this paper, several LNA topologies are presented which can support RX carrier aggregation. Each topology is meticulously characterized in its performance. Simulation results reveal that the cascode divert-switch and cascode-shutoff in common-source configuration shows comparable performance to the legacy operation.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124399738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-power capacitive-feedback CMOS neural recording amplifier for biomedical applications 用于生物医学应用的低功耗电容反馈CMOS神经记录放大器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799786
Hyung Seok Kim, Hyouk-Kyu Cha
{"title":"A low-power capacitive-feedback CMOS neural recording amplifier for biomedical applications","authors":"Hyung Seok Kim, Hyouk-Kyu Cha","doi":"10.1109/ISOCC.2016.7799786","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799786","url":null,"abstract":"A low-power capacitive-feedback amplifier IC for neural SoCs in medical implant devices using 0.18μm CMOS technology is presented. The proposed neural amplifier, which is based on the source-degenerated folded-cascoded OTA, achieves 40 dB of voltage gain and integrated input-referred noise of 4.3 μVrms in the range of 1 Hz to 10 kHz while dissipating 2.2 μA of current from a 1 V supply. The designed amplifier IC achieves the noise efficiency factor of 3.07 and occupies 0.136 mm2 of area.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121961688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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