Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip

Abstract

Network-on-chip (NoC) is being considered as a promising model to overcome the communication bottleneck of future multicore systems. It plays an important role in determining the area and power of the entire chip. As a basic component in on-chip router, arbiter has a large impact on the performance of router. A centralized arbiter called switch arbiter resolves conflicts between the input ports to get the access for the same output port. The design of such power and area efficient switch arbiter for Network on Chip is a major challenge in DSM technology. This paper proposes a novel switch arbiter that reduces power dissipation and consumes less area in comparison to conventional switch arbiter. The novel switch arbiter has been designed using twisted ring counter instead of ring counter to increase its performance. Simulation results have been carried out using Cadence Design Framework with 180nm technology.