2008 Asia and South Pacific Design Automation Conference最新文献_第2页

Architecture-level thermal behavioral characterization for multi-core microprocessors 多核微处理器的体系结构级热行为表征

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483994

Duo Li, S. Tan, M. Tirumala

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引用次数: 13

Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees 基于集合分区和斯坦纳树的特定应用的片上网络体系结构综合

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483955

Shan Yan, Bill Lin

{"title":"Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees","authors":"Shan Yan, Bill Lin","doi":"10.1109/ASPDAC.2008.4483955","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483955","url":null,"abstract":"This paper considers the problem of synthesizing application-specific network-on-chip (NoC) architectures. We propose two heuristic algorithms called CLUSTER and DECOMPOSE that can systematically examine different set partitions of communication flows, and we propose Rectilinear-Steiner-tree (RST) based algorithms for generating an efficient network topology for each group in the partition. Different evaluation functions in fitting with the implementation backend and the corresponding implementation technology can be incorporated into our solution framework to evaluate the implementation cost of the set partitions and RST topologies generated. In particular, we experimented with an implementation cost model based on the power consumption parameters of a 70 nm process technology where leakage power is a major source of energy consumption. Experimental results on a variety of NoC benchmarks showed that our synthesis results can on average achieve a 6.92 x reduction in power consumption over the best standard mesh implementation. To further gauge the effectiveness of our heuristic algorithms, we also implemented an exact algorithm that enumerates all distinct set partitions. For the benchmarks where exact results could be obtained, our CLUSTER and DECOMPOSE algorithms on average can achieve results within 1% and 2% of exact results, with execution times all under 1 second whereas the exact algorithms took as much as 4.5 hours.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116595295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

Automatic re-coding of reference code into structured and analyzable SoC models 将参考代码自动重新编码为结构化和可分析的SoC模型

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483991

Pramod Chandraiah, R. Dömer

引用次数: 10

Heuristic power/ground network and floorplan co-design method 启发式电源/地网与平面图协同设计方法

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484025

Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong

引用次数: 5

Block cache for embedded systems 嵌入式系统的块缓存

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483967

Dominic Hillenbrand, J. Henkel

引用次数: 3

Automatic generation of hardware dependent software for MPSoCs from abstract system specifications 基于抽象系统规范的mpsoc硬件相关软件的自动生成

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483954

G. Schirner, A. Gerstlauer, R. Dömer

引用次数: 27

A low-cost cryptographic processor for security embedded system 一种用于安全嵌入式系统的低成本密码处理器

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483921

Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, L. Mai, Jia Zhao

引用次数: 9

Statistical power profile correlation for realistic thermal estimation 统计功率分布相关性的实际热估计

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484038

L. Singhal, Sejong Oh, E. Bozorgzadeh

引用次数: 7

Total power optimization combining placement, sizing and multi-Vt through slack distribution management 通过松弛分布管理，实现布局、尺寸和多vt相结合的总功率优化

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483973

T. Luo, D. Newmark, D. Pan

{"title":"Total power optimization combining placement, sizing and multi-Vt through slack distribution management","authors":"T. Luo, D. Newmark, D. Pan","doi":"10.1109/ASPDAC.2008.4483973","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483973","url":null,"abstract":"Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power and timing are often conflicting objectives during optimization. In this paper, we propose a novel total power optimization flow under performance constraint. Instead of using placement, gate sizing, and multiple-Vt assignment techniques independently, we combine them together through the concept of slack distribution management to maximize the potential for power reduction. We propose to use the linear programming (LP) based placement and the geometric programming (GP) based gate sizing formulations to improve the slack distribution, which helps to maximize the total power reduction during the Vt-assignment stage. Our formulations include important practical design constraints, such as slew, noise and short circuit power, which were often ignored previously. We tested our algorithm on a set of industrial-strength manually optimized circuits from a multi-GHz 65 nm microprocessor, and obtained very promising results. To our best knowledge, this is the first work that combines placement, gate sizing and Vt swapping systematically for total power (and in particular leakage) management.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128158059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering 基于时序和逻辑滤波的耦合感知静态时序分析中的悲观情绪降低

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483999

D. Das, Kip Killpack, Chandramouli V. Kashyap, A. Jas, H. Zhou

引用次数: 5