2008 Asia and South Pacific Design Automation Conference最新文献_第10页

Scheduling with integer time budgeting for low-power optimization 基于整数时间预算的低功耗优化调度

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483947

Wei Jiang, Zhiru Zhang, M. Potkonjak, J. Cong

引用次数: 24

A new low energy BIST using a statistical code 基于统计码的新型低能量物理标准技术

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484031

S. Chun, Taejin Kim, Sungho Kang

引用次数: 12

Super-K: A SoC for single-chip ultra mobile computer Super-K:用于单芯片超移动计算机的SoC

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483957

Xu Cheng

引用次数: 2

Interconnect modeling for improved system-level design optimization 互连建模改进系统级设计优化

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483952

L. Carloni, A. Kahng, S. Muddu, A. Pinto, K. Samadi, P. Sharma

{"title":"Interconnect modeling for improved system-level design optimization","authors":"L. Carloni, A. Kahng, S. Muddu, A. Pinto, K. Samadi, P. Sharma","doi":"10.1109/ASPDAC.2008.4483952","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483952","url":null,"abstract":"Accurate modeling of delay, power, and area of interconnections early in the design phase is crucial for effective system-level optimization. Models presently used in system-level optimizations, such as network-on-chip (NoC) synthesis, are inaccurate in the presence of deep-submicron effects. In this paper, we propose new, highly accurate models for delay and power in buffered interconnects; these models are usable by system-level designers for existing and future technologies. We present a general and transferable methodology to construct our models from a wide variety of reliable sources (Liberty, LEF/ITF, ITRS, PTM, etc.). The modeling infrastructure, and a number of characterized technologies, are available as open source. Our models comprehend key interconnect circuit and layout design styles, and a power-efficient buffering technique that overcomes unrealities of previous delay-driven buffering techniques. We show that our models are significantly more accurate than previous models for global and intermediate buffered interconnects in 90 nm and 65 nm foundry processes - essentially matching signoff analyses. We also integrate our models in the COSI-OCC synthesis tool and show that the more accurate modeling significantly affects optimal/achievable architectures that are synthesized by the tool. The increased accuracy provided by our models enables system-level designers to obtain better assessments of the achievable performance/power/area tradeoffs for (communication-centric aspects of) system design, with negligible setup and overhead burdens.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127057266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Efficient synthesis of compressor trees on FPGAs fpga上压缩树的高效合成

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483927

H. Parandeh-Afshar, P. Brisk, P. Ienne

引用次数: 63

Reaching the limits of low power design 达到低功耗设计的极限

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484048

J. Hobbs, T. Williams

引用次数: 1

Block remap with turnoff: A variation-tolerant cache design technique 带关闭的块重映射:一种容错缓存设计技术

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484058

M. A. Hussain, M. Mutyam

{"title":"Block remap with turnoff: A variation-tolerant cache design technique","authors":"M. A. Hussain, M. Mutyam","doi":"10.1109/ASPDAC.2008.4484058","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484058","url":null,"abstract":"With reducing feature size, the effects of process variations are becoming more and more predominant. Memory components such as on-chip caches are more susceptible to such variations because of high density and small sized transistors present in them. Process variations can result in high access latency and leakage energy dissipation. This may lead to a functionally correct chip being rejected, resulting in reduced chip yield. In this paper, by considering a process variation affected on-chip data cache, we first analyze performance loss due to worst-case design techniques such as accessing the entire cache with the worst-case access latency or turning off the process variation affected cache blocks, and show that the worst-case design techniques result in significant performance loss and/or high leakage energy. Then by exploiting the fact that not all applications require full associativity at set-level, we propose a variation-tolerant design technique, namely, block remap with turnoff (BRT), to minimize performance loss and leakage energy consumption. In BRT technique we selectively turnoff few blocks after rearranging them in such a way that all sets get almost equal number of process variation affected blocks. By turning off process variation affected blocks of a set, leakage energy can be minimized and the set can be accessed with low latency at the cost of reduced set associativity. We validate our technique by running SPEC2000 CPU benchmark-suite on Simplescalar simulator and show that our technique significantly reduces the performance loss and leakage energy consumption due to process variations.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124458503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages 双层球栅阵列封装单调经分配的可达性驱动修正方法

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483949

Yoichi Tomioka, A. Takahashi

引用次数: 11

A brand new wireless day 崭新的无线一天

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483940

J. Rabaey

{"title":"A brand new wireless day","authors":"J. Rabaey","doi":"10.1109/ASPDAC.2008.4483940","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483940","url":null,"abstract":"Summary form only given. The wireless communications field has experienced a truly amazing growth since the early 1990's. Wireless connectivity slowly but surely has become pervasive. One would expect that by now this revolution must be losing some steam, but the truth is far from that. If anything, it is gathering even more speed. In the coming decades, introduction of innovative wireless technologies will enable a broad range of exciting applications to come to fruition, and reshape the way we interact with our daily living environment. Underlying it all is a three-tiered environment consisting of a large number of huge data and compute centers, billions of mobile compute and computation devices, and potentially trillions of tiny sensors and actuators. Making this happen will require some important wireless roadblocks to be either overcome or circumvented. A short list of those includes spectrum scarcity, reliability, complexity, security and obviously power. In this presentation, a number of innovative and even revolutionary solutions to address these will be discussed. Examples are collaborative cognitive networks, wireless in the mm-wave region of the spectrum, and miniature wireless. Each of these approaches pushes some part of the design technology to its limits, and may even require a totally novel approach towards design, all this while semiconductor technology is trying to cope with the uncertainty of design in the nanometer regime. One thing is for sure - the wireless designer of the next decade is bound for some very exciting times.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"565 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor 用于微处理器/微控制器/DSP处理器的参数化嵌入式仿真器及其可重定向调试软件

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483923

Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang

引用次数: 4