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2007 IEEE Design and Diagnostics of Electronic Circuits and Systems最新文献

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On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata 基于sat - lp的线性混合自动机有界模型检验中的变量选择
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295318
Marc Herbstritt, B. Becker, E. Ábrahám, Christian Herde
{"title":"On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata","authors":"Marc Herbstritt, B. Becker, E. Ábrahám, Christian Herde","doi":"10.1109/DDECS.2007.4295318","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295318","url":null,"abstract":"One approach for the verification of embedded systems, where discrete control is embedded in a continuous environment, is bounded model checking of linear hybrid automata. As a decision procedure within this context, a combination of a propositional SAT-solver and an LP-solver can be used. For such combined SAT-LP solvers, it is, among others, an open question how a robust, i.e., reliable, variable selection heuristics should be designed. In this work we investigate the design of such heuristics taking into account (1) the algorithmic structure of the combined SAT-LP-solver, and (2) efficiency issues in form of a counter-based design that adapts the popular concept of the VSIDS heuristics of Chaff. An empirical analysis of our framework shows (1) the importance of guard variables related to real-valued constraints and (2) reveals an ambiguity between the number of calls of the LP-solver and the time used by the LP-solver. As a result, we propose a simple, but efficient, variable selection heuristics that takes our observations into account and experimentally overcomes the limitations of existing ones.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123735486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation 基于新功耗模型的低功耗双电平逻辑综合
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295269
I. Brzozowski, A. Kos
{"title":"Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation","authors":"I. Brzozowski, A. Kos","doi":"10.1109/DDECS.2007.4295269","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295269","url":null,"abstract":"Accurate analysis of CMOS gate power dissipation shows that amount of consumed energy depends on a reason of the gate switching. Number of activated inputs and type of applied signals have an influence on dynamic power dissipation of the gate due to dynamic reconfiguration of internal gate parasitic capacitors. Therefore, authors propose new modeling of dynamic power dissipation in static CMOS gates. Accurate modeling of dynamic power dissipation needs to take into consideration changes of all input signals. So, authors introduce new measure of digital circuit activity - gate driving way - for precise modeling of power dissipation. Based on conclusions flowing from the model analysis, authors propose method for two-level low-power circuits design.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"91 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114050039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories CRF: SRAM存储器中复杂读错误的有效测试
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295276
L. Dilillo, B. Al-Hashimi
{"title":"March CRF: an Efficient Test for Complex Read Faults in SRAM Memories","authors":"L. Dilillo, B. Al-Hashimi","doi":"10.1109/DDECS.2007.4295276","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295276","url":null,"abstract":"In this paper we study complex read faults in SRAMs, a combination of various malfunctions that affect the read operation in nanoscale memories. All the memory elements involved in the read operation are studied, underlining the causes of the realistic faults concerning this operation. The requirements to cover these fault models are given. We show that the different causes of read failure are independent and may coexist in nanoscale SRAMs, summing their effects and provoking complex read faults, CRFs. We show that the test methodology to cover this new read faults consists in test patterns that match the requirements to cover all the different simple read fault models (non-destructive). We propose a low complexity (~2N) test, March CRF, that covers effectively all the realistic complex read faults.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121332866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Novel Parity Bit Scheme for SBox in AES Circuits AES电路中一种新的SBox奇偶校验位方案
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295295
G. D. Natale, M. Flottes, B. Rouzeyre
{"title":"A Novel Parity Bit Scheme for SBox in AES Circuits","authors":"G. D. Natale, M. Flottes, B. Rouzeyre","doi":"10.1109/DDECS.2007.4295295","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295295","url":null,"abstract":"This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only to protect the encryption/decryption process from random and production faults. It will also protect the system against side-channel attacks, in particular fault-based attacks, i.e. the injection of faults in order to retrieve the secret key. We will prove that our solution is very effective while keeping the area overhead very low.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121820121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization 时域DRM信号识别算法及硬件实现
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295297
L. Ruckay, J. Nedved
{"title":"Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization","authors":"L. Ruckay, J. Nedved","doi":"10.1109/DDECS.2007.4295297","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295297","url":null,"abstract":"This article presents a new algorithm for DRM (digital radio Mondiale) signal recognition. Such an algorithm is useful for fast scanning and classifying broadcast transmission, which is our goal. The algorithm which we have presented in (Ruckay, 2006) works in frequency domain and is based on a processing of spectrum properties. The recognition algorithm presented here works in time domain and takes advantage of signal time structure. The new algorithm is nearly three times faster and its HW demands are evidently smaller in the comparison with the previous one (Ruckay, 2006). A basic introduction into relevant parts of the DRM standard is given and an efficient implementation of the introduced algorithm is described as well. We also provide results of live radio frequency scanning test where our algorithm shows recognition score higher than 90%.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121434215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips 将互联网连接快速集成到片上系统的设计平台
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295252
B. Wojciechowski, T. Kowalczyk, W. Sakowski
{"title":"Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips","authors":"B. Wojciechowski, T. Kowalczyk, W. Sakowski","doi":"10.1109/DDECS.2007.4295252","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295252","url":null,"abstract":"The paper describes pre-integrated subsystem consisting of a configurable 8-bit microcontroller and an Internet connection solution. The latter integrates Ethernet Media Access Controller, hardware accelerator that implements TCP/IP checksums generation and analysis and the third party TCP/IP stack adapted to take advantage of the available accelerator. A reference design based on the presented subsystem is also described. It enables interaction with the object controlled by microcontroller by means of a web browser.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121316525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters 基于递归移动的分层聚类分区优化
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295288
R. Bazylevych, Ihor Podolskyy, L. Bazylevych
{"title":"Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters","authors":"R. Bazylevych, Ihor Podolskyy, L. Bazylevych","doi":"10.1109/DDECS.2007.4295288","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295288","url":null,"abstract":"The paper presents a general approach for partitioning optimization based on the hierarchical clustering by the optimal circuit reduction (OCR) method. This method has proved to be robust, effective and efficient tool to identify the hierarchical clusters circuit structure. For initial partitioning and its optimization the optimal circuit reduction trees are used. Recursive moves (transfers and exchanges) of hierarchically built clusters and their groups of arbitrary sizes are performed for optimization. Some new efficient procedures to escape from the local optima are suggested.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Test Pattern Generator for Delay Faults 延迟故障测试模式发生器
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295293
T. Rudnicki, A. Hlawiczka
{"title":"Test Pattern Generator for Delay Faults","authors":"T. Rudnicki, A. Hlawiczka","doi":"10.1109/DDECS.2007.4295293","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295293","url":null,"abstract":"One of the recently proposed solutions to the problem generation of test pairs' patterns to target delay faults is a multiple input signature register (MISR). The paper proposes a method to minimize control words and to modify the operation diagram of the test pattern generator (TPG) aiming at achieving acceptable test times while ensuring a very high coverage of delay faults. Experimental results are presented, in which the method of test pairs for benchmarks of the ISCAS'89 has been employed.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131234802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Establishing a New Course in Reconfigurable Logic System Design 建立可重构逻辑系统设计新课程
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295286
J. Tørresen, Jorgen Norendal, K. Glette
{"title":"Establishing a New Course in Reconfigurable Logic System Design","authors":"J. Tørresen, Jorgen Norendal, K. Glette","doi":"10.1109/DDECS.2007.4295286","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295286","url":null,"abstract":"Reconfigurable computing has grown to become important in hardware design. In autumn 2005, we taught for the first time a new course in digital system design with its main focus on FPGA technology and design using VHDL. This paper reports about the various issues dealt with including what topics to cover, text book selection, lab exercises etc. A summary of the students feedback is also included.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132653344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
IP Integration Overhead Analysis in System-on-Chip Video Encoder 片上系统视频编码器的IP集成开销分析
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295306
Antti Rasmus, A. Kulmala, E. Salminen, T. Hämäläinen
{"title":"IP Integration Overhead Analysis in System-on-Chip Video Encoder","authors":"Antti Rasmus, A. Kulmala, E. Salminen, T. Hämäläinen","doi":"10.1109/DDECS.2007.4295306","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295306","url":null,"abstract":"Current system-on-chip implementations integrate IP blocks from different vendors. Typical problems are incompatibility and integration overheads. This paper presents a case study of integrating two black-box hardware accelerators into highly scalable and modular multiprocessor system-on-chip architecture. The integration was implemented by creating two wrapper components that adapt the interfaces of the hardware accelerators for the used architecture and on-chip network. The benefit of the accelerators was measured in three different configurations and especially the execution time overheads caused by the software, data delivery, and shared resource contention were extracted and analyzed in MPEG-4 encoder. The overheads increase the function runtime up to 20x compared to the ideal acceleration. In addition, the accelerator that seemed to be more efficient performed worse in practice. As a conclusion, it is pointed out that the integration induces great overhead to the execution time, rendering a-few-clock-cycle optimizations within the accelerator meaningless.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114521648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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