Test Pattern Generator for Delay Faults

Abstract

One of the recently proposed solutions to the problem generation of test pairs' patterns to target delay faults is a multiple input signature register (MISR). The paper proposes a method to minimize control words and to modify the operation diagram of the test pattern generator (TPG) aiming at achieving acceptable test times while ensuring a very high coverage of delay faults. Experimental results are presented, in which the method of test pairs for benchmarks of the ISCAS'89 has been employed.