2007 IEEE Design and Diagnostics of Electronic Circuits and Systems最新文献

Dedicated architecture for double precision matrix multiplication in supercomputing environment 超级计算环境下双精度矩阵乘法专用体系结构

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295303

P. Russek, K. Wiatr

引用次数: 7

A proposal for ASM++ diagrams 一个关于ASM++图的建议

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295265

S. Pablo, S. Cáceres, J. Cebrián, Manuel Berrocal

引用次数: 7

Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System 容错可重构双工系统的故障注入与仿真

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295312

P. Kubalík, J. Kvasnicka, H. Kubátová

引用次数: 6

Flip-Flops and Scan-Path Elements for Nanoelectronics 纳米电子学的触发器和扫描路径元件

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295301

R. Kothe, H. Vierhaus

引用次数: 4

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing 避免串扰对互连延迟故障测试的影响

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295271

T. Garbolino, K. Gucwa, M. Kopec, A. Hlawiczka

引用次数: 0

MEMS Testing by Vibrating Capacitor 基于振动电容的MEMS测试

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295324

J. Mizsei, M. Reggente

引用次数: 2

Feasibility of Image Compression in FPGA based Neural Networks 基于FPGA的神经网络图像压缩的可行性

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295305

Vladimir Havel, K. Vlcek

引用次数: 1

Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application 用于医疗诊断的无线数据采集射频系统的仿真与特性研究

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295268

K. Arshak, F. Adepoju, E. Jafer

引用次数: 2

Test Pattern Compression Based on Pattern Overlapping 基于模式重叠的测试模式压缩

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295250

Jiri Jenícek, O. Novák

{"title":"Test Pattern Compression Based on Pattern Overlapping","authors":"Jiri Jenícek, O. Novák","doi":"10.1109/DDECS.2007.4295250","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295250","url":null,"abstract":"This paper describes a test data compression method based on pattern overlapping. We report here improvements that have been done on the test pattern compaction and compression algorithm called COMPAS. This algorithm reorders and compresses test patterns previously generated in an ATPG in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. It compresses the test patterns by overlapping patterns originally generated by an ATPG. The problem of the COMPAS algorithm is that it has to manipulate with enormous amount of data when compressing test sets of large circuits and the CPU time grows rapidly with the growing number of test vectors. These disadvantages were solved by using a test vector initial encoding by sparse vectors and by using a dynamic structure for storing the pre-calculated parameters of candidate vectors to be used in the near future algorithm loops for overlapping with the actual scan chain content. This arrangement allows the algorithm to skip unnecessary computations. The improvements cause that the CPU time grows approximately linearly with the size of the tested circuit. The improved algorithm is also capable to compress data generated by concurrently working ATPG processes.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116475808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs 基于可重构fpga的自修复耐辐射实现框架

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295300

M. Gericota, Luís F. Lemos, G. Alves, J. Ferreira

{"title":"A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs","authors":"M. Gericota, Luís F. Lemos, G. Alves, J. Ferreira","doi":"10.1109/DDECS.2007.4295300","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295300","url":null,"abstract":"To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129363493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5