2007 IEEE Design and Diagnostics of Electronic Circuits and Systems最新文献_第3页

Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's 利用FPGA的嵌入式存储块实现顺序电路的低成本综合

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295261

G. Borowik, B. Falkowski, T. Luba

引用次数: 22

Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits 异步准延迟不敏感组合电路的冗余和测试模式生成

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295316

A. Efthymiou

引用次数: 7

Debug Patterns for Efficient High-level SystemC Debugging 高效的高级SystemC调试模式

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295320

Frank Rogin, Erhard Fehlauer, Christian Haufe, Sebastian Ohnewald

引用次数: 4

ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing 集成电路ESD故障及其传输线脉冲诊断

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295323

Z. Piatek, J. Kolodziejski, W. Pleskacz

引用次数: 3

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor 高性能区间算术处理机加乘单元的设计

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295285

A. Amaricai, M. Vladutiu, L. Prodan, M. Udrescu, O. Boncalo

{"title":"Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor","authors":"A. Amaricai, M. Vladutiu, L. Prodan, M. Udrescu, O. Boncalo","doi":"10.1109/DDECS.2007.4295285","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295285","url":null,"abstract":"This paper proposes a new approach for the optimization process of the interval addition and multiplication floating point units. For the interval addition/subtraction, an adder exploiting the parallelism of the double path adder structure is used. The two floating point additions needed are performed simultaneously on different data paths. Therefore, the performance of the proposed adder can be the same as that of two individual floating point adders, but with a much reduced cost overhead. Regarding the interval multiplication, a multiplier architecture was designed, in order to be suitable for pipelined structures. It consists of a floating point multiplier which computes two results for the same operation (rounded differently), and of two floating point comparators. In terms of performance, the proposed multiplier unit presents half of the performance of a conventional floating point multiplier. This is not a drawback, if we consider the fact that interval multiplication requires four floating point operations and six comparisons. This paper shows that interval arithmetic can be efficiently implemented in terms of performance and cost.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124958491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair facility via Variable Accuracy Arithmetic 基于变精度算法的嵌入式自修复专用处理器VLIW体系结构的提出

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295302

P. Pawlowski, A. Dabrowski, Mario Schölzel

{"title":"Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair facility via Variable Accuracy Arithmetic","authors":"P. Pawlowski, A. Dabrowski, Mario Schölzel","doi":"10.1109/DDECS.2007.4295302","DOIUrl":"https://doi.org/10.1109/DDECS.2007.4295302","url":null,"abstract":"A new proposal of a very long instruction word (VLIW) architecture for application specific processors with the built-in-self-repair (BISR) facility realized by means of the variable accuracy arithmetic has been described in this paper. The proposed idea, which is particularly interesting for the portable embedded systems, is based on a novel two accumulator model, which is used in order to obtain high accuracy of the result of a series of floating-point additions. The goal of the proposed approach consists in ensuring the functionality of the system even in case of permanent faults of particular building blocks, e.g., of one of the floating point adders. Instead of decreasing the performance of the system or providing redundant hardware, as it is typically done in other approaches, in our present concept merely the accuracy of the floating point accumulation is reduced. Therefore, although the quality of service is reduced, the performance and the overall functionality of the system may remain unchanged. By this means we can also control the power consumption, saving the power with the cost of the somehow reduced signal processing accuracy.","PeriodicalId":274042,"journal":{"name":"2007 IEEE Design and Diagnostics of Electronic Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121588631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Parts Obsolescence Challenges for the Electronics Industry 电子工业零件过时的挑战

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295267

J. Tørresen, T. Lovland

引用次数: 17

RF Transformer Model Parameters Measurement 射频变压器模型参数测量

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295298

V. Dumbrava, L. Svilainis

引用次数: 1

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services 一种减少实时操作系统服务中软错误影响的软硬件架构

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295291

Mohammad Hossein Neishaburi, M. R. Kakoee, M. Daneshtalab, S. Safari, Z. Navabi

引用次数: 7

Decomposition of Logic Functions in Reed-Muller Spectral Domain Reed-Muller谱域逻辑函数的分解

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems Pub Date : 2007-04-11 DOI: 10.1109/DDECS.2007.4295284

E. Hrynkiewicz, S. Kolodzinski

引用次数: 8