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2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)最新文献

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An inductive system for measuring microampere currents 一种测量微安培电流的感应系统
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384375
C. Cirstea, M. Cernaianu, A. Gontean
{"title":"An inductive system for measuring microampere currents","authors":"C. Cirstea, M. Cernaianu, A. Gontean","doi":"10.1109/SIITME.2012.6384375","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384375","url":null,"abstract":"This paper describes an inductive current measurement system (ICMS) which has been developed and used for measuring currents down to the μA scale. The need for such a measurement system came from an experimental setup developed with the purpose of determining the performance of a P2110 radio frequency energy harvesting board in terms of output power. The main components of the ICMS are two LTS 15-NP Hall effect current transducers. The measured signal is driven through one the transducers while the other transducer is used as reference. Both outputs are filtered and fed into an AD8230 rail-to-rail precision instrumentation amplifier (INA). The output of the INA is low pass filtered and fed into a National Instruments (NI) USB 6251 data acquisition system (DAQ). The DAQ is driven by a NI LabVIEW 2009 interface which performs system calibration based on a compensation table that contains the transducer output volt-current analogy and also performs current measurement. The entire system is battery powered and enclosed in a brass casing to reduce external magnetic interferences.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132698103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Conductive layer deposition and peel tests on biodegradable printed circuit boards 生物可降解印刷电路板的导电层沉积和剥离试验
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384363
A. Géczy, M. Kovács, I. Hajdu
{"title":"Conductive layer deposition and peel tests on biodegradable printed circuit boards","authors":"A. Géczy, M. Kovács, I. Hajdu","doi":"10.1109/SIITME.2012.6384363","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384363","url":null,"abstract":"Biodegradable plastics are novel materials which can be degraded by organic methods. The aim of the work was to investigate the usability of a cellulose-acetate (CA) and a polylactide (PLA) based material as a printed circuit board (PCB) with conductive layer peel tests. The common types of conductive layer coating processes were proposed: copper foil lamination, copper electroplating and thick film conductive layer deposition. The paper focuses solely of copper foil lamination. The laminates were examined by optical microscopy. The copper layer peel tests were mainly used to determine the bonding strength of the conductive layer, according to the instructions of IPC-TM-650 standard. Future investigations will involve application and test of the other conductive layer deposition processes, also the possible soldering methods, and thermal stability of the biodegradable PCBs.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114597079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Condensation model of Vapour Phase Soldering 气相焊接的冷凝模型
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384347
B. Illés, A. Géczy
{"title":"Condensation model of Vapour Phase Soldering","authors":"B. Illés, A. Géczy","doi":"10.1109/SIITME.2012.6384347","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384347","url":null,"abstract":"This paper presents a modeling approach of vapour condensation during the Vapour Phase Soldering (VPS) process at board level. This model is based on a process (machine) level model which calculates the vapour and temperature space in the VPS tank. The board level condensation model is embedded into the process level model (presented in [1]). The condensation model applies combined transport mechanisms including heat transport by heat conduction; mass transport by phase change during the condensation of the Galden liquid; and energy transport caused by mass transport. The model uses a special dew point calculation which was defined for Galden liquid by experiments. The model can describe the temperature change of the soldered assembly and transmit data to the process level model. This way the effect of the soldered assembly on the vapour space can be investigated.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127204669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Software in the Loop environment reliability for testing embedded code 软件在循环环境中测试嵌入式代码的可靠性
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384402
M. Muresan, D. Pitica
{"title":"Software in the Loop environment reliability for testing embedded code","authors":"M. Muresan, D. Pitica","doi":"10.1109/SIITME.2012.6384402","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384402","url":null,"abstract":"This paper makes an analysis of the Software in the Loop (SiL) environment reliability for testing embedded system algorithms. The embedded system used during this analysis was developed around a C167CR microcontroller and based on a real-time (RT) operating system (OS). The main function of the control algorithm implemented into the embedded system is to control the speed of a DC motor. The embedded system software was wrapped into a SiL environment where the real-time operating system and the low level drivers where emulated. The obtained results where compared with the ones from Hardware in the Loop (HiL) testing system. Several aspects were followed during analysis: accuracy of the obtained results, proper functioning of the emulated RT OS, the possibility of using the same tools over product life cycle and implementation of automated.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125252109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Dynamic measurement circuit for the resistive transducers 电阻式传感器的动态测量电路
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384387
S. Pop, V. Bande, D. Pitica, I. Ciascai
{"title":"Dynamic measurement circuit for the resistive transducers","authors":"S. Pop, V. Bande, D. Pitica, I. Ciascai","doi":"10.1109/SIITME.2012.6384387","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384387","url":null,"abstract":"This paper is focused on measurement of the resistive transducers used in dam's monitoring process. The hydro-energetic buildings, like dams are equipped with a large type of resistive transducer. Some of the sensors are placed inside during the dam construction, but, sensors are also mounted later on. The dams are monitored with a large type of resistive transducers. The first generations contain 40Ω and new sensor generations have 5k Ω. The main aim of this paper is to develop a measurement circuit that allows measuring all resistive sensors using the same circuit. The proposed circuit excites the transducer with a constant current. The signal acquisition is made with a programmable gain amplifier (PGA). The resistive transducer is measured in the useful range using a relative voltage on one of the PDA inputs. The relative voltage is generated with a digital analog converter (DAC). The measurement circuit it's a feedback complex structure. The measurement value is obtained sequentially in several steps. The central unit of measurement device is a microcontroller; the systematic error can be compensated soft. Through a careful selection of electronics components like resistors and reference voltages, the measurement accuracy is 0.1%.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116374084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison between two Surface Insulation Resistance tests regarding different soldering techniques 两种不同焊接技术的表面绝缘电阻测试的比较
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384366
M. Pantazica, C. Marghescu, P. Svasta, G. Vărzaru, I. Plotog, C. Tămaş
{"title":"Comparison between two Surface Insulation Resistance tests regarding different soldering techniques","authors":"M. Pantazica, C. Marghescu, P. Svasta, G. Vărzaru, I. Plotog, C. Tămaş","doi":"10.1109/SIITME.2012.6384366","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384366","url":null,"abstract":"The paper shows the results of a second approach of the Surface Insulation Resistance (SIR) test performed in order to test the quality of solder pastes. The aim of the SIR test was to establish the influence of the reflow method used and of a protective coating on the SIR. At the end of this test, a comparison between the obtained results was done. Both tests were done in the conditions of environment heat and high humidity. The boards used in both experiments are special designed test pattern boards (IPC-B-24) and the no-clean solder pastes are the following: SAC305, SN100C, SN100C-XF3 OM338PT, OM5300 [1]. The measurements of the SIR values showed better results keeping in mind that this was the second experiment and that we gained experience during the first experiment.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131875677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficiency evaluation via finite element method of 3D magnetostatic shields using different types of magnetic potentials 三维静磁屏蔽在不同磁势下的效能有限元评估
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384340
D. Cazacu, Ș. Castravete
{"title":"Efficiency evaluation via finite element method of 3D magnetostatic shields using different types of magnetic potentials","authors":"D. Cazacu, Ș. Castravete","doi":"10.1109/SIITME.2012.6384340","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384340","url":null,"abstract":"The efficiency of spherical and cylindrical magnetic shields placed in a magnetostatic field are modeled numerically, with FEM, taking into account: a) type of magnetic potential: scalar or vector; b) for certain types of shields comparisons with the measured values will be performed; c) comparison between analytical values and numerical values. It is a beginning of a study which will continue with the study shielding efficiency at low and high frequencies respectively.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130948123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Thermal modeling and analysis of a power device heat sinks 功率器件散热器的热建模与分析
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384379
C. Farcas, I. Ciocan, D. Petreus, N. Palaghita
{"title":"Thermal modeling and analysis of a power device heat sinks","authors":"C. Farcas, I. Ciocan, D. Petreus, N. Palaghita","doi":"10.1109/SIITME.2012.6384379","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384379","url":null,"abstract":"This paper presents a study about thermal behavior of heat sink - power device assembly. The power device (power transistor, triac, thyristor etc) and the heat sink were modeled in SolidWorks. These models have been used in simulations. We take into consideration different power devices packages, different heat sinks and different thermally conductive pastes. A thermal analysis has been performed by position of heat sink on PCB. In our study, we have taken into consideration the influence of the holes from heat sink in heat dissipations. The results of simulations and experimental measurements realized with a temperature data logger are presented in the paper.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A MATLAB tool to optimize the selection of the decoupling capacitors in a PDN 一个优化PDN中去耦电容选择的MATLAB工具
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384380
R. Fizesan, O. Pop
{"title":"A MATLAB tool to optimize the selection of the decoupling capacitors in a PDN","authors":"R. Fizesan, O. Pop","doi":"10.1109/SIITME.2012.6384380","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384380","url":null,"abstract":"For a good reliability, the Power Distribution Network (PDN) should meet target impedance across the frequency range of direct current, up to the highest frequency of interest. Using decoupling capacitors is a good mean to maintain the impedance of a PDN below a specified level, [3][4][5]. Decoupling capacitors are used to obtain low power supply impedance in the MHz range. Decoupling capacitors have traditionally been modeled as a series RLC network. Capacitors vendors describe the specifications in terms of its capacitance, equivalent series inductance and equivalent series resistance. The RLC components are constant with frequency and are easily identified in the Bode plot. There are several commercial tools available to help in selecting the decoupling capacitors, but the goal of this paper is to present a MATLAB tool that helps us reduce the time of simulations and optimize the process of selecting the decoupling capacitors.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134183265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Current distortions compensation method for frequency converters 变频器电流畸变补偿方法
2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME) Pub Date : 2012-12-24 DOI: 10.1109/SIITME.2012.6384356
Ioan Orha, Stefan Oniga
{"title":"Current distortions compensation method for frequency converters","authors":"Ioan Orha, Stefan Oniga","doi":"10.1109/SIITME.2012.6384356","DOIUrl":"https://doi.org/10.1109/SIITME.2012.6384356","url":null,"abstract":"This paper present a study of the effects of frequency converters to the power grid and a possible solution for current distortions compensation. Experimental measurements made, at different points of the grid, with the device Fluke 434 to a converter which supplies a 110 kW asynchronous motor, reveal the distortions of current. Harmonics content of current for the three phases and THD distortion factor emphasize the existence of strong distortions of current. Current compensation method, proposed and simulated, consists in collecting a sample of non-sinusoidal current from the inverter input resistance or using a current transformer, which will be decreased from a sinusoidal reference signal. This difference is amplified and synchronized, so that it can be injected back into the grid. Simulations above described method are made in Matlab-Simulink Power Systems.","PeriodicalId":273985,"journal":{"name":"2012 IEEE 18th International Symposium for Design and Technology in Electronic Packaging (SIITME)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134099527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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