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2010 27th International Conference on Microelectronics Proceedings最新文献

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Photothermal elastic vibration spectra of SiO2 film on Si 硅表面SiO2薄膜的光热弹性振动谱
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490490
D. Todorović, B. Cretin, Y. Song, V. Jović
{"title":"Photothermal elastic vibration spectra of SiO2 film on Si","authors":"D. Todorović, B. Cretin, Y. Song, V. Jović","doi":"10.1109/MIEL.2010.5490490","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490490","url":null,"abstract":"The silicon-dioxide film on the silicon substrate (SiO2 / Si) samples were investigated by the photothermal elastic vibration method. The photothermal elastic vibrations in two-layer rectangular plates were optically excited by the focused laser beam and the generated vibrations were measured with a sensitive optical probe (the double-heterodyne interferometer). The photothermal elastic vibrations spectra were measured and analyzed for different types of Si substrate (with and without the SiO2 films) vs the frequency of modulation of the excitation laser. This investigation is important for analysis of the influence of the different technological processes to the vibrations of the optically driven micromechanical structures, i.e. how the technological processes change the characteristics of micromechanical structures.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"458 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125829575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Voltage scaling limitations and challenges of memory-rich nanoscale CMOS LSIs 富存储纳米级CMOS lsi的电压缩放限制和挑战
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490536
K. Itoh, R. Tsuchiya
{"title":"Voltage scaling limitations and challenges of memory-rich nanoscale CMOS LSIs","authors":"K. Itoh, R. Tsuchiya","doi":"10.1109/MIEL.2010.5490536","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490536","url":null,"abstract":"The minimum operating voltage, V<inf>min</inf>, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate V<inf>min</inf>. It shows that V<inf>min</inf> is very sensitive to the threshold-voltage variations, ΔV<inf>t</inf>, which become more significant with device scaling, and to the lowest necessary threshold voltage, V<inf>t0</inf>, of MOSFETs. As a result of comparing the V<inf>min</inf>S of logic, SRAM, and DRAM blocks, it turns out that the SRAM block is problematic because it has the highest V<inf>min</inf> despite using RAM repair techniques. Various techniques are thus reviewed, including shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To further reduce the V<inf>min</inf>S of the blocks, ΔV┌immune MOSFETs such as a planar fully-depleted structure (FD-SOI) and fin-type structure (FinFET), and low-V<inf>t0</inf> circuits are discussed, showing the below 0.5-V era feasible to come.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115374989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Accelerating first-time-right high-speed system designs with high-performance FPGAs 利用高性能fpga加速首次正确的高速系统设计
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490463
Sven-Hendrik Voss, Michael Schueler, Michael Baerwolff, Markus Kranz, Sebastian Dreßler
{"title":"Accelerating first-time-right high-speed system designs with high-performance FPGAs","authors":"Sven-Hendrik Voss, Michael Schueler, Michael Baerwolff, Markus Kranz, Sebastian Dreßler","doi":"10.1109/MIEL.2010.5490463","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490463","url":null,"abstract":"Realizing maximum performance from FPGA-based printed circuit board (PCB) designs requires close attention to the employed technology, board-level interconnections and circuit design. By outlining the design of a high-complexity board, decisive aspects of modern board design are presented, encouraging acceleration in first-time-right high-speed system designs. On the basis of this complex development the acceleration strategies are pointed out. In the development process special attention has been given to “design for testability”.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"598 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116072569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Platinum decoration of silicon direct wafer bonded interfaces 硅直接晶圆键合界面的白金装饰
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490487
D. Valente, N. Batut, L. Ventura
{"title":"Platinum decoration of silicon direct wafer bonded interfaces","authors":"D. Valente, N. Batut, L. Ventura","doi":"10.1109/MIEL.2010.5490487","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490487","url":null,"abstract":"In this paper we investigate the electrical properties of hydrophobic silicon wafer bonded interface. Platinum diffusion, commonly used to enhance fast bipolar P-i-N diodes, is performed to control its electrical properties. The control of the bonded interface properties is a necessary condition to integrate the wafer bonding technique as a new manufacturing process for structures such as bidirectional switch devices. This work is based on spreading Resistance (SR), Deep Level Transient Spectroscopy (DLTS) and Micro-PhotoConductivity Decay (μ-PCD) characterizations of as-bonded and platinum decorated silicon direct wafer bonded interfaces.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133997952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of constant voltage stress in Hf-doped Ta2O5 stacks 恒压应力对hf掺杂Ta2O5电堆的影响
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490437
I. Manic, E. Atanassova, N. Stojadinovic, D. Spassov
{"title":"Effects of constant voltage stress in Hf-doped Ta2O5 stacks","authors":"I. Manic, E. Atanassova, N. Stojadinovic, D. Spassov","doi":"10.1109/MIEL.2010.5490437","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490437","url":null,"abstract":"Conduction mechanisms in Hf-doped Ta2O5 stacks (7; 10 nm) under the constant voltage stress (CVS) are probed by the SILC analysis. The low field conduction is ascribed to trap-assisted tunneling, and the Poole-Frenkel effect dominates at medium and high fields. Stress affects the pre-existing traps and their energy levels, but does not create additional traps. The thinner layers exhibit better temperature and electrical stability after CVS.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131195278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparative studies of single- and double-nanocrystal layer NVM structures: Charge accumulation and retention 单、双纳米晶层NVM结构的比较研究:电荷积累与保留
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490524
V. Turchanikov, V. Ievtukh, A. Nazarov, V. Lysenko, M. Theodoropoulou, A. Nassiopoulou
{"title":"Comparative studies of single- and double-nanocrystal layer NVM structures: Charge accumulation and retention","authors":"V. Turchanikov, V. Ievtukh, A. Nazarov, V. Lysenko, M. Theodoropoulou, A. Nassiopoulou","doi":"10.1109/MIEL.2010.5490524","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490524","url":null,"abstract":"Two types of NC NVM structures had been tested for W/E window formation, charge relaxation and retention. It was shown that the difference between two structures types is significant.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116111331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Determination of recombination centres in c-Si solar cells from dark I-V characteristics 利用暗I-V特性测定c-Si太阳能电池的复合中心
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490511
J. Salinger, V. Benda, Z. Machacek
{"title":"Determination of recombination centres in c-Si solar cells from dark I-V characteristics","authors":"J. Salinger, V. Benda, Z. Machacek","doi":"10.1109/MIEL.2010.5490511","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490511","url":null,"abstract":"The grade of a solar cell depends mainly on the quality of the starting material. During the production of this material, many impurities are left in the bulk material and form defects, which act as generation-recombination centres or charge carrier traps. These defects influence the efficiency of solar cells. Therefore knowledge of the centre parameters, e.g., energy levels in the band gap, capture cross section and concentration, is very useful for solar cell engineering. In this paper emphasis is placed on a simple and fast method for obtaining these parameters using measurements of dark characteristics. Preliminary results are introduced, together with the difficulties and limits of this method.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121572250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of substrate effects inducing non-ideal collector current at low bias 低偏置诱导非理想集电极电流的衬底效应建模
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490527
Daniel P. Vidal, R. van der Toorn
{"title":"Modeling of substrate effects inducing non-ideal collector current at low bias","authors":"Daniel P. Vidal, R. van der Toorn","doi":"10.1109/MIEL.2010.5490527","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490527","url":null,"abstract":"Bipolar junction transistors with a non isolated substrate have extra effects that need to be included in compact models. These effects are due to the existence of a parasitic pnp transistor inside the main transistor having the substrate as its collector. The parasitic can be modeled as a complete transistor, however that would add too much complexity to the whole model. This work focuses on one aspect of the parasitic pnp: the reverse biasing of the collector-substrate junction. This reverse biasing induces currents that are very low (≈ pA) at lower temperatures yet are significant (≈ μA) when the device is heated up to 150°C. With recent interest in new technologies requiring accurate functioning at higher temperatures, the reverse current of the collector substrate junction ceases to be negligible and has to be taken into account. This work studies that effect, and models it in a sufficient way.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129600747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electrical and micromechanical performance of ultrasonically cleaned silicon wafers 超声清洗硅片的电学和微力学性能
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490485
A. Nadtochiy, A. Podolian, V. Kuryliuk, A. Kuryliuk, O. Korotchenkov, J. Schmid, V. Schlosser
{"title":"Electrical and micromechanical performance of ultrasonically cleaned silicon wafers","authors":"A. Nadtochiy, A. Podolian, V. Kuryliuk, A. Kuryliuk, O. Korotchenkov, J. Schmid, V. Schlosser","doi":"10.1109/MIEL.2010.5490485","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490485","url":null,"abstract":"The evolution of the electrical and micromechanical properties of Si wafers subjected to a kHz-frequency ultrasonic treatment in a water-containing ultrasonic cleaning bath is reported. The cleaning stages observed with varying treatment time are discussed. It is believed that, wafer treating during the first ≈ 60 min is capable of removing contaminating particulates from the wafer surface and actives interface dangling bonds. These are leading to a decrease of subsurface resistance towards dislocation displacements as observed by the micro-hardness decrease, affect free carrier migration barriers seen in variations of the I-V barrier heights, and acts as recombination centers resulting in accelerated photovoltage decays. Although an exact mechanism is not yet clarified, a partial healing of the bonds may occur at longer cxcitation times (≈ 60–120 min) thus partially reversing the observed changes.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126956039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An ultimate planar MOS transistor for high-performance applications based on classical and modern techniques 基于经典和现代技术的高性能应用的终极平面MOS晶体管
2010 27th International Conference on Microelectronics Proceedings Pub Date : 2010-05-16 DOI: 10.1109/MIEL.2010.5490453
Jyi-Tsong Lin, Y. Eng, C. Kuo, Po-Hsieh Lin
{"title":"An ultimate planar MOS transistor for high-performance applications based on classical and modern techniques","authors":"Jyi-Tsong Lin, Y. Eng, C. Kuo, Po-Hsieh Lin","doi":"10.1109/MIEL.2010.5490453","DOIUrl":"https://doi.org/10.1109/MIEL.2010.5490453","url":null,"abstract":"An ultimate n-shaped source/drain (π-S/D) metal-oxide semiconductor (MOS) transistor is proposed in this paper. The method used to fabricate the proposed π-S/D transistor is based on both the classical and modern techniques (such as, Si-SiGe epitaxial growth, selective SiGe removal, etc.) that can be controllable and repeatable. Also, a new and simple process without the need of an additional mask to achieve the self-aligned (SA) π-S/D structure is demonstrated and its preliminary characteristics are investigated through three dimensional (3D) numerical simulations.","PeriodicalId":271286,"journal":{"name":"2010 27th International Conference on Microelectronics Proceedings","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121954937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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