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1992 Symposium on VLSI Circuits Digest of Technical Papers最新文献

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A neural network embedded processor with a dynamically reconfigurable pipeline architecture 一种具有动态可重构流水线结构的神经网络嵌入式处理器
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229257
T. Satonaka, Y. Tamura, T. Morishita, A. Inoue, S. Katsu, T. Otsuki, G. Kano
{"title":"A neural network embedded processor with a dynamically reconfigurable pipeline architecture","authors":"T. Satonaka, Y. Tamura, T. Morishita, A. Inoue, S. Katsu, T. Otsuki, G. Kano","doi":"10.1109/VLSIC.1992.229257","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229257","url":null,"abstract":"A neural network embedded processor with a dynamically reconfigurable pipeline architecture is described. The processor dynamically changes connections between arithmetic units and memories to obtain the optimum pipeline configuration at every step of the network calculation. The processor attains a learning speed of 18 million connection updates per second (MCUPS), which is approximately 20 times that of the conventional digital signal processor. This processor provides expansibility in the calculation through a larger multilayer network by means of a network decomposition and a distributed processing approach.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124884542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.6 mu m CMOS SOG with a 5 V/3.3 V interfaces 一个0.6 μ m CMOS SOG, 5v /3.3 V接口
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229290
M. Ohkawa, T. Takahashi, M. Yamagishi, Y. Sonobe, N. Ejima
{"title":"A 0.6 mu m CMOS SOG with a 5 V/3.3 V interfaces","authors":"M. Ohkawa, T. Takahashi, M. Yamagishi, Y. Sonobe, N. Ejima","doi":"10.1109/VLSIC.1992.229290","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229290","url":null,"abstract":"A 510-kG CMOS sea-of-gates (SOG) was experimentally developed using 0.6- mu m triple-metal-layer process technology and a 5-V/3.3-V interface. High-speed ASICs for high-performance processor systems supporting both TTL level and LVTTL level interfaces were developed. The 5-V/3.3-V interface concept employs a CMOS buffer on p-substrate, to choose an output high level of either 3.3 V or 5 V. The typical delay times of the internal gate and output buffer are 0.2 ns and 1.3 ns, respectively.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122485669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Circuit techniques for multi-bit parallel testing of 64 Mb DRAMs and beyond 64兆及以上dram的多位并行测试电路技术
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229240
T. Sakuta, M. Muranaka, H. Matsuura, H. Tanaka, Y. Nakagome, K. Miyazawa, M. Ishihara
{"title":"Circuit techniques for multi-bit parallel testing of 64 Mb DRAMs and beyond","authors":"T. Sakuta, M. Muranaka, H. Matsuura, H. Tanaka, Y. Nakagome, K. Miyazawa, M. Ishihara","doi":"10.1109/VLSIC.1992.229240","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229240","url":null,"abstract":"Through the use of a high-speed compression circuit that can compress data signals of low amplitude, high-speed 32-b parallel processing tests for 64 MDRAMs have been achieved. Through the use of a low-power dynamic-type differential amplifier, highly compressed 128-b parallel processing tests have been made possible. By including appropriate test circuits based on independent concepts corresponding to the testing of the peripheral circuits and that of the memory cell, the testing function of 64 MDRAMs has become practical. Design features and characteristics of the 64 MDRAM are summarized.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131945670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 35 ns 64 Mb DRAM using on-chip boosted power supply 采用片上增强电源的35 ns 64 Mb DRAM
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229238
Dong-Jae Lee, Yong-Sik Seok, Do-Chan Choi, Jae-Hyeong Lee, Young-Rae Kim, Hyeun-Su Kim, Dong-Soo Jun, O. Kwon
{"title":"A 35 ns 64 Mb DRAM using on-chip boosted power supply","authors":"Dong-Jae Lee, Yong-Sik Seok, Do-Chan Choi, Jae-Hyeong Lee, Young-Rae Kim, Hyeun-Su Kim, Dong-Soo Jun, O. Kwon","doi":"10.1109/VLSIC.1992.229238","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229238","url":null,"abstract":"An on-chip boosted power supply is necessary for ease of layout and high speed in high density DRAMs. The technique of TTL conversion is a key to designing high speed DRAMs for 3-V operation. The authors present the generation and regulation of an on-chip power supply (V/sub pp/) within 50 mV of the optimum level during operation for a given V/sub cc/. In addition to the regulated V/sub cc/ scheme, improved interface circuit techniques are employed to achieve fast input and output conversion with good noise margins. An experimental 64-Mb DRAM is designed. A typical access time of 35 ns is obtained by measurement.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131613590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 6 ns 1 Mb CMOS SRAM with high-performance sense amplifier 具有高性能感测放大器的6ns 1mb CMOS SRAM
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229253
T. Seki, E. Itoh, C. Furukawa, I. Maeno, T. Ozawa, H. Sano, N. Suzuki, Y. Matsukawa
{"title":"A 6 ns 1 Mb CMOS SRAM with high-performance sense amplifier","authors":"T. Seki, E. Itoh, C. Furukawa, I. Maeno, T. Ozawa, H. Sano, N. Suzuki, Y. Matsukawa","doi":"10.1109/VLSIC.1992.229253","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229253","url":null,"abstract":"A 1-Mb (256 K*4) SRAM with an access time of 6 ns using a 0.5- mu m CMOS technology is described. Fast access and low power dissipation are achieved by using a new nMOS source-controlled latched sense amplifier and a data output pre-reset circuit that reduces the output transition time.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116187886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low power 12 b analog-to-digital converter with on-chip precision trimming 一个低功耗12b模数转换器，具有片上精密微调
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229272
M. Dewit, K. Tan, R. Hester
{"title":"A low power 12 b analog-to-digital converter with on-chip precision trimming","authors":"M. Dewit, K. Tan, R. Hester","doi":"10.1109/VLSIC.1992.229272","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229272","url":null,"abstract":"The design and performance of a 12 b charge redistribution ADC is described. The architecture is chosen to minimize conversion time and power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a linear 1 mu m CMOS process. The die area, including the 12 b parallel digital interface is 15 kmil/sup 2/. The power dissipation is under 15 mW, making the energy per conversion only 45 nJ.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129290447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new on-chip voltage regulator for high density CMOS DRAMs 一种用于高密度CMOS dram的新型片上稳压器
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229268
R. S. Mao, H. Chao, Y. Chi, P.W. Chung, C. Hsieh, C.M. Lin, N. Lu, S.Y. Lan, Y.F. Liu, M. Lin, D. Wang, H. Tuan, H. Tsai, C. Lu
{"title":"A new on-chip voltage regulator for high density CMOS DRAMs","authors":"R. S. Mao, H. Chao, Y. Chi, P.W. Chung, C. Hsieh, C.M. Lin, N. Lu, S.Y. Lan, Y.F. Liu, M. Lin, D. Wang, H. Tuan, H. Tsai, C. Lu","doi":"10.1109/VLSIC.1992.229268","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229268","url":null,"abstract":"The authors report on new voltage regulator circuitry used in a 4 Mb CMOS DRAM. The DRAM accepts a 5 V external power supply and generates 3.3 V on chip. The chip photomicrograph is provided with a magnified portion of the regulator. The internal voltage V/sub INT/ is regulated at 3.3 V (25 degrees C), while V/sub DD/ varies from 3.3 to 6.2 V. V/sub INT/ presents a positive temperature coefficient, which is adjustable, to compensate the higher cell leakage and the slowdown of MOSFET operations at higher temperature. While V/sub DD/ is raised above 6.3 V, the regulator enters the burn-in mode where V/sub INT/ follows a 2/3 V/sub DD/ curve, which gives an exact internal burn-in voltage as desired. This internal burn-in voltage is insensitive to temperature and process variations.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Application of a high-voltage pumped supply for low-power DRAM 高压泵浦电源在低功耗DRAM中的应用
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229269
R. Foss, G. Allan, P. Gillingham, F. Larochelle, V. Lines, G. Shimokura
{"title":"Application of a high-voltage pumped supply for low-power DRAM","authors":"R. Foss, G. Allan, P. Gillingham, F. Larochelle, V. Lines, G. Shimokura","doi":"10.1109/VLSIC.1992.229269","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229269","url":null,"abstract":"A pumped, regulated V/sub pp/ supply feeding static word-line driver circuits can be exploited in other areas of a DRAM, allowing increased flexibility in architecture and improving performance. A feedback loop sets the V/sub pp/ level to exactly that required to write a full '1' level to the memory cell, independent of process or operating condition. The need for double-boosted nodes is eliminated, making the V/sub pp/ level th highest voltage on the chip and easing voltage stress problems. The V/sub pp/ supply is also employed in a modulated input-threshold world-line repeater, which regenerates the world-line signal to overcome RC delay. Significant area savings can be realized in high-density DRAMs by multiplexing sense amplifiers between adjacent arrays, using n-channel isolation devices controlled by V/sub pp/ level signals. A final use of the regulated V/sub pp/ supply is in an n-channel only output buffer achieving full rail-to-rail swing.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134138184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A quick intelligent program architecture for 3 V-only NAND-EEPROMs 一种用于3v -only nand - eeprom的快速智能程序架构
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229256
T. Tanaka, Y. Tanaka, H. Nakamura, H. Oodaira, S. Aritome, R. Shirota, F. Masuoka
{"title":"A quick intelligent program architecture for 3 V-only NAND-EEPROMs","authors":"T. Tanaka, Y. Tanaka, H. Nakamura, H. Oodaira, S. Aritome, R. Shirota, F. Masuoka","doi":"10.1109/VLSIC.1992.229256","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229256","url":null,"abstract":"A quick program/program verify architecture with an intelligent verify circuit for 3-V-only NAND-EEPROMs is described. The verify circuit, which is composed of two transistors, provides a simple, intelligent program algorithm for 3-V-only operation. The total programming time is reduced to 50%. By using intelligent verify circuits, the memory cells which require more time to reach the program state are automatically detected. Verify-read, the modification of program data, and data reload are performed simultaneously. The chip size penalty is estimated to be only 1% for a 16-Mb NAND-EEPROM.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129710853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An 8*8 ATM switch LSI with shared multi-buffer architecture 一种具有共享多缓冲结构的8*8 ATM开关LSI
1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI: 10.1109/VLSIC.1992.229284
H. Notani, H. Kondoh, I. Hayashi, H. Yamanaka, H. Saito, Y. Matsuda, M. Nakaya
{"title":"An 8*8 ATM switch LSI with shared multi-buffer architecture","authors":"H. Notani, H. Kondoh, I. Hayashi, H. Yamanaka, H. Saito, Y. Matsuda, M. Nakaya","doi":"10.1109/VLSIC.1992.229284","DOIUrl":"https://doi.org/10.1109/VLSIC.1992.229284","url":null,"abstract":"An ATM switch LSI with a shared multibuffer architecture is proposed. With this architecture, a fourfold speed improvement is achieved in accessing buffer memories as compared to conventional shared-buffer-type switches, and high buffer memory utilization efficiency is also realized. This switch LSI is designed to operate at 100 MHz, using 0.8- mu m BiCMOS technology. Eight switch LSIs at 78-MHz operation construct a 622-Mb/s 8*8 ATM switching system with a buffer size of 8*128 ATM cells.<<ETX>>","PeriodicalId":269692,"journal":{"name":"1992 Symposium on VLSI Circuits Digest of Technical Papers","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132409468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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