A neural network embedded processor with a dynamically reconfigurable pipeline architecture

T. Satonaka, Y. Tamura, T. Morishita, A. Inoue, S. Katsu, T. Otsuki, G. Kano
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Abstract

A neural network embedded processor with a dynamically reconfigurable pipeline architecture is described. The processor dynamically changes connections between arithmetic units and memories to obtain the optimum pipeline configuration at every step of the network calculation. The processor attains a learning speed of 18 million connection updates per second (MCUPS), which is approximately 20 times that of the conventional digital signal processor. This processor provides expansibility in the calculation through a larger multilayer network by means of a network decomposition and a distributed processing approach.<>
一种具有动态可重构流水线结构的神经网络嵌入式处理器
介绍了一种具有动态可重构流水线结构的神经网络嵌入式处理器。处理器动态地改变运算单元和存储器之间的连接,以在网络计算的每一步获得最佳的管道配置。该处理器的学习速度为每秒1800万次连接更新(MCUPS),大约是传统数字信号处理器的20倍。该处理器通过网络分解和分布式处理方法,通过更大的多层网络提供了计算的可扩展性
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