一个0.6 μ m CMOS SOG, 5v /3.3 V接口

1992 Symposium on VLSI Circuits Digest of Technical Papers Pub Date : 1992-06-04 DOI:10.1109/VLSIC.1992.229290

M. Ohkawa, T. Takahashi, M. Yamagishi, Y. Sonobe, N. Ejima

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引用次数: 0

摘要

采用0.6 μ m三金属层工艺技术和5-V/3.3 v接口，实验研制了510 kg的CMOS海栅(SOG)。为支持TTL和LVTTL级接口的高性能处理器系统开发了高速asic。5v /3.3 V接口概念采用p基板上的CMOS缓冲器，以选择3.3 V或5 V的输出高电平。内部栅极和输出缓冲器的典型延迟时间分别为0.2 ns和1.3 ns。

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A 0.6 mu m CMOS SOG with a 5 V/3.3 V interfaces

A 510-kG CMOS sea-of-gates (SOG) was experimentally developed using 0.6- mu m triple-metal-layer process technology and a 5-V/3.3-V interface. High-speed ASICs for high-performance processor systems supporting both TTL level and LVTTL level interfaces were developed. The 5-V/3.3-V interface concept employs a CMOS buffer on p-substrate, to choose an output high level of either 3.3 V or 5 V. The typical delay times of the internal gate and output buffer are 0.2 ns and 1.3 ns, respectively.<>

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1992 Symposium on VLSI Circuits Digest of Technical Papers

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