A 0.6 mu m CMOS SOG with a 5 V/3.3 V interfaces

Abstract

A 510-kG CMOS sea-of-gates (SOG) was experimentally developed using 0.6- mu m triple-metal-layer process technology and a 5-V/3.3-V interface. High-speed ASICs for high-performance processor systems supporting both TTL level and LVTTL level interfaces were developed. The 5-V/3.3-V interface concept employs a CMOS buffer on p-substrate, to choose an output high level of either 3.3 V or 5 V. The typical delay times of the internal gate and output buffer are 0.2 ns and 1.3 ns, respectively.<>