2017 IEEE International Solid-State Circuits Conference (ISSCC)最新文献_第2页

18.2 Highly-linear integrated magnetic-free circulator-receiver for full-duplex wireless 18.2用于全双工无线的高线性集成无磁环行接收机

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-03-02 DOI: 10.1109/ISSCC.2017.7870388

Negar Reiskarimian, Mahmood Baraani Dastjerdi, Jin Zhou, H. Krishnaswamy

{"title":"18.2 Highly-linear integrated magnetic-free circulator-receiver for full-duplex wireless","authors":"Negar Reiskarimian, Mahmood Baraani Dastjerdi, Jin Zhou, H. Krishnaswamy","doi":"10.1109/ISSCC.2017.7870388","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870388","url":null,"abstract":"A fundamental challenge of full-duplex (FD) wireless [1] is the implementation of low-cost, small-form-factor, integrated shared-antenna (ANT) interfaces with low loss, low noise, high TX-RX isolation, and large TX power handling. Providing more TX-RX isolation in the ANT interface that is robust to environmental variations lowers the self-interference cancellation (SIC) and dynamic range required in the RF, analog baseband (BB), and digital domains. Reciprocal shared-ANT interfaces, such as electrical-balance duplexers [2], fundamentally feature at least 3dB loss (practically >4dB). A non-reciprocal active shared-ANT duplexing scheme was demonstrated in [3], but such active approaches are limited in their maximum supported TX power (−17.3dBm in [3] limited by RX compression) and noise performance. An integrated FD RX with a magnetic-free non-reciprocal passive circulator was demonstrated in [4]. Despite the circulator's low loss and relatively high linearity, the RX could only handle up to −7dBm TX power due to limited circulator isolation and RX LNA linearity. NF under cancellation was also as high as 10.9dB.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127283383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS 8.6一种2.5 ~ 5.75 ghz 5mW 0.3 psmms抖动级联环形数字注入锁定时钟乘法器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-03-02 DOI: 10.1109/ISSCC.2017.7870306

Daniel Coombs, Ahmed Elkholy, R. Nandwana, A. Elmallah, P. Hanumolu

{"title":"8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS","authors":"Daniel Coombs, Ahmed Elkholy, R. Nandwana, A. Elmallah, P. Hanumolu","doi":"10.1109/ISSCC.2017.7870306","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870306","url":null,"abstract":"Ring oscillator (RO)-based clock multipliers are traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter requirements grow more stringent. Recognizing that the main limitation of PLLs arises from limited RO noise suppression bandwidth (NBW = FREF/10), multiplying delay-locked loops (MDLLs) that suppress noise by replacing a RO's noisy edge with a clean reference clock edge have gained prominence [1–3]. Such an edge replacement operation suppresses RO noise with an increased NBW of about FREF/4 [1]. However, imperfections of edge replacement logic have limited the output frequency of MDLLs [1, 2] or degraded their jitter performance at frequencies beyond 2.5GHz [3]. Furthermore, MDLLs are susceptible to transistor non-idealities and require elaborate analog calibration schemes that are prone to circuit imperfections [2, 3]. In contrast to PLLs and MDLLs, injection-locked clock multipliers (ILCMs) lock RO frequency to an integer multiple (N) of FREF by injecting narrow pulses at FREF into the RO whose free running frequency is about NF REF [4]. Because ILCMs do not require logic that needs to adhere to stringent timing requirements (like MDLLs) they are better suited for generating high frequencies. However, their jitter performance is limited by: (i) smaller NBW (≈ FREF/6) compared to MDLLs, (ii) limited suppression of RO flicker noise due to their Type-I response, and (iii) the need for RO free running frequency, FFR, to be close to NFREF for maintaining low jitter performance across voltage and temperature. These factors limit the multiplication factor (usually to less than 10) and degrade power efficiency [4,5]. In this paper, we present an ILCM architecture that achieves a NBW of close to FREF/3 with a jitter of 335fsrms at 5GHz, while operating with FREF = 125MHz and consuming 5.3mW.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129205800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter 5.1 A 5×80W 0.004% THD+N车载多相d类音频放大器，集成低延迟ΔΣ adc，用于输出滤波器后的数字化反馈

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-03-02 DOI: 10.1109/ISSCC.2017.7870273

F. Mostert, D. Schinkel, W. Groothedde, L. Breems, R. V. Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, P. Zeelen, D. Hissink, Martin Pos, P. Wielage, F. Jorritsma, M. K. Middelink

{"title":"5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter","authors":"F. Mostert, D. Schinkel, W. Groothedde, L. Breems, R. V. Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, P. Zeelen, D. Hissink, Martin Pos, P. Wielage, F. Jorritsma, M. K. Middelink","doi":"10.1109/ISSCC.2017.7870273","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870273","url":null,"abstract":"Feedback after the output filter has long been a desired feature for high-power switching (Class-D) amplifiers, as it mitigates the influence of the LC filter components on the frequency transfer function and on linearity, enabling lower component costs. However, it requires compensation of the LC filter to maintain loop stability. In the analog domain, this is difficult to combine with high loop-gain, as the design has to cope with variability in both the LC filter and in the loop-filter. In [1], multiple analog feedback loop-filters from before and after the output filter have been employed, but the loop-gain of the outer loop is only ∼10dB at 20kHz. Alternatively, digital filters have no variability in their coefficients and are well suited for programmable compensation of the output filter, optionally even adaptive. In [2] feasibility is shown of a single digital loop with full global feedback. However, to achieve this, a costly commercially available ADC with 2.5MHz bandwidth and 950mW power consumption was required, a drawback that so far has prevented further adoption. In this paper we present a 5-channel Class-D amplifier with integrated low-latency delta-sigma (ΔΣ) ADCs, each consuming only 30mW, for digital feedback after the output filter. With this system, more than 50dB loop-gain is obtained. THD+N is 0.004% over the full audio band, which is at least 10× better than [1] where data is only given at 1kHz.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123755962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

15.9 An integrated optical physically unclonable function using process-sensitive sub-wavelength photonic crystals in 65nm CMOS 15.9采用65nm CMOS制程敏感亚波长光子晶体的集成光学物理不可克隆函数

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-03-02 DOI: 10.1109/ISSCC.2017.7870366

Xuyang Lu, Lingyu Hong, K. Sengupta

{"title":"15.9 An integrated optical physically unclonable function using process-sensitive sub-wavelength photonic crystals in 65nm CMOS","authors":"Xuyang Lu, Lingyu Hong, K. Sengupta","doi":"10.1109/ISSCC.2017.7870366","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870366","url":null,"abstract":"Physical unclonable function (PUF) is regarded as an emerging solution for reliable cryptography. Rather than storing secret keys in memories, the information of a PUF is extracted through amplification of the physically uncontrollable process variations and therefore, can uniquely authenticate each die to counteract counterfeit, piracy or sabotage. Classically, PUF architectures have exploited process variations affecting transistor-level active device performances such as process-dependent gate delays and interconnect delays, SRAM and inverter maximum gain points, and ring oscillator frequencies [1]–[6]. While active device variations have been exploited to generate PUF signatures, they are susceptible to noise, external perturbations and aging. Since the resultant process variant responses are typically normally distributed, to spread the variance of the distribution and decrease the number of challenges near the unstable decision region, we propose a method to exploit passive variations within the chip in addition to active device variations. While lithographic variations in the smallest metal features may not influence the electrical performance drastically, their effects can be amplified at optical frequencies with wavelengths comparable to the minimal feature size. In fact, before the concept of electronic PUFs were demonstrated in silicon, one of the first implementations of strong PUFs was demonstrated in the optical domain, which exploited speckle-patterns of a random scattering medium in the presence of a laser light. In this work, we present the first CMOS-based opto-active PUF, which not only utilizes the active variations, but also amplifies the lithographic variation of passive metal structures through process-sensitive copper-based CMOS integrated photonic crystals. The measured CMOS chip achieves a native Inter-PUF/Intra-PUF Hamming Distance (HD) ratio of 198X without any post-operation.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124694827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification 21.6基于频域特征提取和SVM分类的12nW恒在线声传感与目标识别微系统

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-03-02 DOI: 10.1109/ISSCC.2017.7870411

Seokhyeon Jeong, Yu Chen, Taekwang Jang, J. M. Tsai, D. Blaauw, Hun-Seok Kim, D. Sylvester

{"title":"21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification","authors":"Seokhyeon Jeong, Yu Chen, Taekwang Jang, J. M. Tsai, D. Blaauw, Hun-Seok Kim, D. Sylvester","doi":"10.1109/ISSCC.2017.7870411","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870411","url":null,"abstract":"IoT devices are becoming increasingly intelligent and context-aware. Sound is an attractive sensory modality because it is information-rich but not as computationally demanding as alternatives such as vision. New applications of ultra-low power (ULP), ‘always-on’ intelligent acoustic sensing includes agricultural monitoring to detect pests or precipitation, infrastructure health tracking to recognize acoustic symptoms, and security/safety monitoring to identify dangerous conditions. A major impediment for the adoption of always-on, context-aware sensing is power consumption, particularly for ultra-small IoT devices requiring long-term operation without battery replacement. To sustain operation with a 1mm2 solar cell in ambient light (100lux) or achieve a lifetime of 10 years using a button cell battery (2mAh), <20nW power consumption must be achieved, which is more than 2 orders of magnitude lower than current state-of-the-art acoustic sensing systems [1,2]. More broadly a previous ULP signal acquisition IC [3] consumes just 3nW while 64nW ECG monitoring system [4] includes back-end classification, however there are no sub-20nW complete sensing systems with both analog frontend and digital backend.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114600406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

17.9 A 105Gb/s 300GHz CMOS transmitter 17.9 105Gb/s 300GHz CMOS发射机

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-03-02 DOI: 10.1109/ISSCC.2017.7870384

K. Takano, S. Amakawa, K. Katayama, S. Hara, R. Dong, A. Kasamatsu, I. Hosako, K. Mizuno, Kazuaki Takahashi, T. Yoshida, M. Fujishima

引用次数: 74

24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radio 24.3高线性CMOS接收器，实现+44dBm IIP3和+13dBm B1dB，用于无saw LTE无线电

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-08 DOI: 10.1109/ISSCC.2017.7870436

Yuanching Lien, E. Klumperink, B. Tenbroek, J. Strange, B. Nauta

引用次数: 53

5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop 带过程诱导频率误差补偿回路的正交弛豫振荡器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-07 DOI: 10.1109/ISSCC.2017.7870277

Jahyun Koo, K. Moon, Byungsub Kim, Hong-June Park, J. Sim

{"title":"5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop","authors":"Jahyun Koo, K. Moon, Byungsub Kim, Hong-June Park, J. Sim","doi":"10.1109/ISSCC.2017.7870277","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870277","url":null,"abstract":"With the emergence of wearable and implantable technologies, there has been growing demand on development of key enabling circuits for ultra-low-power sensor interface SoCs. As a reference-frequency generation block for clock management of the overall system, the relaxation oscillator has been widely adopted since it can provide a controllable and well-defined untrimmed frequency with low-cost circuits. In the past decade, the major goal in the design of the relaxation oscillators has been the improvement of phase-noise figure-of-merit (FOM) closer to the fundamental limit of 169dBc/Hz [1]. There have been feedback approaches to internally generate reference voltages for comparison, hence compensating the comparator circuit delay [2–4]. Since the delay compensation relies on the feedback operation, power consumption by analog circuits to meet the required bandwidth of the feedback loop eventually limits FOM. Recently, a swing-boosted differential scheme was proposed to reduce the effect of comparator noise by boosting the signal slope at the comparator input, demonstrating an FOM of over 160dBc/Hz [5]. However, the boosted voltage swing can increase stress on the input transistors of the comparator. In addition, a high-speed comparator is also needed to reduce the effect of the circuit delay on the output frequency. While most of previous works achieved good FOMs with MHz oscillators, implementation of low-frequency relaxation oscillators presents additional challenges since it requires excessive area for RC and power consumption by analog circuits with leakage not scaled down along with the output frequency.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122485484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit 5.8 9.3nW一体化带隙电压电流参考电路

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-07 DOI: 10.1109/ISSCC.2017.7870280

Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, J. Sim

{"title":"5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit","authors":"Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, J. Sim","doi":"10.1109/ISSCC.2017.7870280","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870280","url":null,"abstract":"Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124153635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 69

3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOI 3.6 A 60pJ/b 300Mb/s 128×8 28nm FD-SOI大规模MIMO预编码检测器

2017 IEEE International Solid-State Circuits Conference (ISSCC) Pub Date : 2017-02-03 DOI: 10.1109/ISSCC.2017.7870260

H. Prabhu, J. Rodrigues, Liang Liu, O. Edfors

引用次数: 38