8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS

Daniel Coombs, Ahmed Elkholy, R. Nandwana, A. Elmallah, P. Hanumolu
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引用次数: 34

Abstract

Ring oscillator (RO)-based clock multipliers are traditionally used for clocking digital systems such as processors. While they are most commonly implemented using PLLs, it is becoming increasingly difficult to design them in a power efficient manner, as their jitter requirements grow more stringent. Recognizing that the main limitation of PLLs arises from limited RO noise suppression bandwidth (NBW = FREF/10), multiplying delay-locked loops (MDLLs) that suppress noise by replacing a RO's noisy edge with a clean reference clock edge have gained prominence [1–3]. Such an edge replacement operation suppresses RO noise with an increased NBW of about FREF/4 [1]. However, imperfections of edge replacement logic have limited the output frequency of MDLLs [1, 2] or degraded their jitter performance at frequencies beyond 2.5GHz [3]. Furthermore, MDLLs are susceptible to transistor non-idealities and require elaborate analog calibration schemes that are prone to circuit imperfections [2, 3]. In contrast to PLLs and MDLLs, injection-locked clock multipliers (ILCMs) lock RO frequency to an integer multiple (N) of FREF by injecting narrow pulses at FREF into the RO whose free running frequency is about NF REF [4]. Because ILCMs do not require logic that needs to adhere to stringent timing requirements (like MDLLs) they are better suited for generating high frequencies. However, their jitter performance is limited by: (i) smaller NBW (≈ FREF/6) compared to MDLLs, (ii) limited suppression of RO flicker noise due to their Type-I response, and (iii) the need for RO free running frequency, FFR, to be close to NFREF for maintaining low jitter performance across voltage and temperature. These factors limit the multiplication factor (usually to less than 10) and degrade power efficiency [4,5]. In this paper, we present an ILCM architecture that achieves a NBW of close to FREF/3 with a jitter of 335fsrms at 5GHz, while operating with FREF = 125MHz and consuming 5.3mW.
8.6一种2.5 ~ 5.75 ghz 5mW 0.3 psmms抖动级联环形数字注入锁定时钟乘法器
基于环形振荡器(RO)的时钟乘法器传统上用于时钟数字系统,如处理器。虽然它们通常使用锁相环实现,但随着它们的抖动要求变得越来越严格,以节能的方式设计它们变得越来越困难。认识到锁相环的主要限制来自于有限的RO噪声抑制带宽(NBW = FREF/10),乘法延迟锁定环(mdls)通过用干净的参考时钟边缘替换RO的噪声边缘来抑制噪声已经得到了重视[1-3]。这样的边缘替换操作抑制了RO噪声,NBW增加了约FREF/4[1]。然而,边缘替换逻辑的缺陷限制了mdls的输出频率[1,2],或者降低了它们在2.5GHz以上频率下的抖动性能[3]。此外,mdl易受晶体管非理想性的影响,需要精心设计的模拟校准方案,容易出现电路缺陷[2,3]。与pll和mdll相比,注入锁定时钟乘法器(ilcm)通过向自由运行频率约为NF REF的RO注入FREF的窄脉冲,将RO频率锁定为FREF的整数倍[4]。由于ilcm不需要需要遵守严格时序要求的逻辑(如mdll),因此它们更适合产生高频。然而,它们的抖动性能受到以下因素的限制:(i)与mdls相比,NBW更小(≈FREF/6), (ii)由于它们的i型响应,对RO闪烁噪声的抑制有限,以及(iii) RO自由运行频率FFR需要接近NFREF,以保持跨电压和温度的低抖动性能。这些因素限制了乘数因子(通常小于10)并降低了功率效率[4,5]。在本文中,我们提出了一种ILCM架构,该架构在5GHz时实现了接近FREF/3的NBW,抖动为335fsrms,同时工作在FREF = 125MHz,功耗为5.3mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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