Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test最新文献_第6页

A frequency-domain detection and estimation scheme for single-tone interference suppression 一种单音干扰抑制的频域检测与估计方案

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834920

Hung-Chin Wang

{"title":"A frequency-domain detection and estimation scheme for single-tone interference suppression","authors":"Hung-Chin Wang","doi":"10.1109/VLSI-DAT.2014.6834920","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834920","url":null,"abstract":"For wideband communication systems, the ability against relatively narrowband interference, which is commonly modeled as single-tone interference, is of great importance. Without proper mitigation, i.e., interference suppression, the system performance can degrade significantly as the interference power increases. To cope with this problem, this paper develops an efficient frequency-domain single-tone interference detection and estimation scheme for interference suppression. After transforming the received signal to frequency domain via fast Fourier transform, and with possible power accumulation of consecutive fast Fourier transform windows for successful detection of relatively weak interference (e.g., at a signal-to-interference ratio around 24dB), we derive the probability density function of the received power within each tone and develop a threshold-based detection scheme, where the theoretical probabilities of false alarm and missed detection given a chosen threshold are also derived and confirmed by simulations. Based on the theoretical analyses, we further propose a high-accuracy and low-complexity scheme that estimates the frequency of single-tone interference.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125079152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

C3Map and ARPSO based mapping algorithms for energy-efficient regular 3-D NoC architectures 基于C3Map和ARPSO的节能规则三维NoC架构映射算法

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834909

Kartikeya Bhardwaj, P. Mane

引用次数: 13

Low-complexity architecture for Chase soft-decision Reed-Solomon decoding Chase软判决Reed-Solomon解码的低复杂度架构

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834896

Y. Lu, Shen-Ming Chung, Ming-Der Shieh

引用次数: 0

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition 高效节能低噪声16通道模拟前端生物电位采集电路

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834893

Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, J. Chiou, Kuo-Hua Chen, C. Chiu, H. Tong, C. Chuang, W. Hwang

引用次数: 5

Efficient test length reduction techniques for interposer-based 2.5D ICs 基于中间体的2.5D集成电路的有效测试长度缩减技术

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834878

Shyue-Kung Lu, Huai-Min Li, M. Hashizume, Jin-Hua Hong, Zheng-Ru Tsai

{"title":"Efficient test length reduction techniques for interposer-based 2.5D ICs","authors":"Shyue-Kung Lu, Huai-Min Li, M. Hashizume, Jin-Hua Hong, Zheng-Ru Tsai","doi":"10.1109/VLSI-DAT.2014.6834878","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834878","url":null,"abstract":"Three-dimensional integration is considered a promising solution to cure the challenges of performance, power consumption, quality, and reliability issues. The feature of 2.5D ICs is that the dies are stacked on a passive silicon interposer and the dies communicate with each other by means of TSV-based interconnects and re-Distribution layers (RDL) within the silicon interposer. This paper aims to investigate the efficient post-bond test technique for the 2.5D ICs with silicon interposer. In order to efficiently reuse the functional interconnects as the parallel TAM (test access mechanism) for testing dies, a novel macro-die-based interconnect reuse strategy and its corresponding design-for-test (DFT) architecture are proposed in this paper. The proposed strategy merges several dies to form a macro die and then connected to other dies to form a daisy chain for testing. Experimental results show that the proposed techniques have higher success rates for the required TAM width constraints. Moreover, since we can get wider TAMs, the test length then can be reduced significantly.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131058880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A hardware-friendly method for rate-distortion optimization of HEVC intra coding 一种硬件友好的HEVC帧内编码率失真优化方法

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834898

W. Shen, Yibo Fan, Leilei Huang, Jiali Li, Xiaoyang Zeng

引用次数: 13

Smart feature detection device for cloud based video recognition system 用于云视频识别系统的智能特征检测装置

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834914

T. Ikenaga, Takahiro Suzuki

{"title":"Smart feature detection device for cloud based video recognition system","authors":"T. Ikenaga, Takahiro Suzuki","doi":"10.1109/VLSI-DAT.2014.6834914","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834914","url":null,"abstract":"Potential of a cloud system combining a smart device and cloud servers is increasing. One of the representative examples is \"Siri\" which offers a friendly web knowledge navigator based on natural language user interface. Since latest portable devices equip not only a microphone but also a high resolution camera, this kind of cloud based framework is also promising to create various kinds of video based recognition systems. There are two essential components for it: a smart device with a high-resolution camera which is responsible for detecting feature from input video and cloud servers which execute recognition or data search using big data as shown in Fig. 1. This paper describes some key technologies of implementing a smart device for a cloud based recognition system. First, a low complexity SIFT (Scale-invariant feature transform) [1] based key point extraction algorithm and its hardware engine capable of operating at full-HD 60fps video [2] are described. As a technique to reduce network bandwidth, a keypoint of interest (KOI) detection algorithm based on spatio-temporal feature considering mutual dependency and camera motion [3] is also discussed. Finally, some promising application examples are shown.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130155315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Precision material engineering — An equipment point of view 精密材料工程。设备的观点

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834926

Mei Chang

引用次数: 0

An all-digital delay-locked loop for high-speed memory interface applications 用于高速存储器接口应用的全数字延迟锁定环路

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834900

Shih-Lun Chen, Ming-Jing Ho, Yuxiu Sun, Maung Wai Lin, Jung-Chin Lai

引用次数: 11

Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier 使用简化的正则符号数字乘法器的可编程FIR滤波器的复杂性-有效实现

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI: 10.1109/VLSI-DAT.2014.6834886

Kuo-Chiang Chang, C. Lin, Chih-Wei Liu

引用次数: 4