W. Shen, Yibo Fan, Leilei Huang, Jiali Li, Xiaoyang Zeng
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引用次数: 13
摘要
与现有的MPEG-4、H.263和H.264/AVC等视频编码标准相比，HEVC (High Efficiency Video coding，高效视频编码)是下一代编码标准，旨在提供显著改进的压缩性能。速率失真优化(RDO)模式决策工具已被证明是极其重要的。由于内预测方向数量的增加以及编码单元(CU)、预测单元(PU)和变换单元(TU)的庞大，RDO过程所涉及的数量急剧增加，这是一个非常耗时和计算量巨大的过程。在本文中，我们提出了一个基于四像素条的ESAD和基于量化TU系数的线性模型来分别估计RD成本函数的失真和率部分。实验结果表明，所提出的RD代价函数在硬件设计中面积减少85.8%，吞吐量提高1260%，比特率和PSNR的损失可以忽略不计。
A hardware-friendly method for rate-distortion optimization of HEVC intra coding
The next generation standard of coding, High Efficiency Video Coding (HEVC) aims to provide significantly improved compression performance in comparison with all existing video coding standards, such as MPEG-4, H.263, and H.264/AVC. The tool of rate-distortion optimization (RDO) mode decision has proven to be extremely important. Due to the increase in the number of intra prediction directions and large size of coding unit (CU), prediction unit (PU) and transform unit (TU), the number involved in RDO process rises dramatically, which is an extremely timing-and-computation-consuming process. In this paper, we propose a four-pixel-strip based ESAD and quantized TU coefficients based linear model to estimate the distortion and rate part of the RD cost function respectively. Experimental results show that the proposed RD cost function provides 85.8% area reduction and 1260% throughput improvement in hardware design, with negligible loss of bitrate and PSNR.
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