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Proceedings of the 2014 IEEE Students' Technology Symposium最新文献

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Synthesis of simultaneous sum and difference patterns in uniformly excited time-modulated linear arrays using firefly algorithm 用萤火虫算法合成均匀激励时调制线性阵列中同时和和差图
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6807930
Ananya Mukherjee, S. K. Mandal, G. K. Mahanti, R. Ghatak
{"title":"Synthesis of simultaneous sum and difference patterns in uniformly excited time-modulated linear arrays using firefly algorithm","authors":"Ananya Mukherjee, S. K. Mandal, G. K. Mahanti, R. Ghatak","doi":"10.1109/TECHSYM.2014.6807930","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807930","url":null,"abstract":"In this paper, sideband radiations which are generally regarded as the undesired effects of time-modulated antenna arrays (TMAAs), are exploited to design multi-beam antenna arrays. Time modulation (TM) is applied into uniformly excited linear array of half wave dipole radiators to generate low side-lobe sum and difference patterns at the center frequency and first sideband respectively while the maximum power level at the higher sidebands are suppressed significantly by optimizing the periodical on-off switching instants of the antenna elements by using fire-fly algorithm (FA). The FA optimized pattern as realized in MATLAB platform is validated by designing the uniformly excited time modulated linear array (UE-TMLA) in CST-MWS with the same on-time sequence as obtained by using FA and the patterns are compared.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116484147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparative analysis of single span high speed 40 Gbps long haul optical link using different modulation formats in the presence of Kerr nonlinearity 克尔非线性下不同调制格式的单跨高速40gbps长途光链路的比较分析
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6807928
Ankit Patel, R. B. Patel, Kinjal A Mehta
{"title":"Comparative analysis of single span high speed 40 Gbps long haul optical link using different modulation formats in the presence of Kerr nonlinearity","authors":"Ankit Patel, R. B. Patel, Kinjal A Mehta","doi":"10.1109/TECHSYM.2014.6807928","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807928","url":null,"abstract":"Rapid increase of the data traffic in communication world has accelerated the development of high capacity long-haul optical links, and the main barrier across these links are the chromatic dispersion and various nonlinear effects. This paper examines the long distance optical link up to 4000 km in the presence of Kerr nonlinearity using various modulation formats using three dispersion compensation schemes at different transmission distances. Here comparative analysis is carried out for the 40 Gbps long haul optical link using carrier-suppressed return to zero (CSRZ), modified duo binary return to zero (MDRZ) and differential phase shift keying (DPSK) modulation formats. The effect of change in the input power and transmission distance is observed in terms of Q value, BER and eye opening of various formats. It is observed that the performance of the system is greatly deteriorated by the Chromatic Dispersion and DPSK modulation format comes out to be the best choice for the long distance transmission up to 4000 km and beyond. Also the pre, post and symmetrical analysis is also carried out for all three modulation formats and optimum results are achieved with the symmetric configuration.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125802328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A simplified space vector PWM scheme for any N-level inverter 一个简化的空间矢量PWM方案，适用于任何n电平逆变器
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6808042
P. M. Shereef, G. Shiny
{"title":"A simplified space vector PWM scheme for any N-level inverter","authors":"P. M. Shereef, G. Shiny","doi":"10.1109/TECHSYM.2014.6808042","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808042","url":null,"abstract":"A simplified space-vector pulse width modulation (SVPWM) scheme for any N-level inverter is presented. The method involves the conversion of space vector diagram of NN-level inverter to that of a 2-level inverter. 60° coordinate system is used to represent space vectors instead of using cartesian coordinate system. In 60° coordinate system only integer coordinates are involved. So the computational complexity is reduced. The proposed scheme is experimentally verified for a three level inverter realised by cascading two 2-level inverters.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125058189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Synthesis of ESOP-based reversible logic using negative polarity reed-muller form 利用负极性reed-muller形式合成基于esop的可逆逻辑
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1007/978-81-322-1817-3_36
Chandan Bandyopadhyay, S. Roy, L. Biswal, H. Rahaman
{"title":"Synthesis of ESOP-based reversible logic using negative polarity reed-muller form","authors":"Chandan Bandyopadhyay, S. Roy, L. Biswal, H. Rahaman","doi":"10.1007/978-81-322-1817-3_36","DOIUrl":"https://doi.org/10.1007/978-81-322-1817-3_36","url":null,"abstract":"","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116873913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA based implementation & power analysis of parameterized Walsh sequences 基于FPGA的参数化Walsh序列实现及功耗分析
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6808063
Gaurav Purohit, V. K. Chaubey, K. Raju, D. Vyas
{"title":"FPGA based implementation & power analysis of parameterized Walsh sequences","authors":"Gaurav Purohit, V. K. Chaubey, K. Raju, D. Vyas","doi":"10.1109/TECHSYM.2014.6808063","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808063","url":null,"abstract":"This paper presents FPGA based implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions i.e. Walsh function. The paper further compares Parameterized `Serial In Serial Out' architectures based on classical counter approach. The investigation consider FPGA parameters like Area, Speed and Power and shows that using Gray-increment based architecture instead of Binary saves 6mW of power per symbol (64 Walsh chips per symbol) with 30% reduction in area. The design is implemented in VHDL code, simulated in MATLAB System Generator environment and validated with MATLAB Simulink Model. The design targeted Xilinx Virtex-5 “XC5VLX50T-1ff1136” FPGA device for the implementation and comparison. The design found their uses in many popular applications like Software Define Radio (SDR) including multiuser communications such as CDMA, WCDMA, VLSI testing, pattern recognition as well as image and signal processing.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121991520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel approach for image compression based on multi-level image thresholding using Shannon Entropy and Differential Evolution 基于Shannon熵和差分进化的多级图像阈值压缩新方法
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6807914
S. Paul, B. Bandyopadhyay
{"title":"A novel approach for image compression based on multi-level image thresholding using Shannon Entropy and Differential Evolution","authors":"S. Paul, B. Bandyopadhyay","doi":"10.1109/TECHSYM.2014.6807914","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807914","url":null,"abstract":"Image compression is one of the most important step in image transmission and storage. Most of the state-of-art image compression techniques are spatial based. In this paper, a histogram based image compression technique is proposed based on multi-level image thresholding. The gray scale of the image is divided into crisp group of probabilistic partition. Shannon's Entropy is used to measure the randomness of the crisp grouping. The entropy function is maximized using a popular metaheuristic named Differential Evolution to reduce the computational time and standard deviation of optimized objective value. Some images from popular image database of UC Berkeley and CMU are used as benchmark images. Important image quality metrics-PSNR, WPSNR and storage size of the compressed image file are used for comparison and testing. Comparison of Shannon's entropy with Tsallis Entropy is also provided. Some specific applications of the proposed image compression algorithm are also pointed out.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125624268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
An automated method for detecting systolic peaks from arterial blood pressure signals 一种从动脉血压信号中检测收缩压峰值的自动方法
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6807911
Dandu Sriram Raju, M. Manikandan, Ramkumar Barathram
{"title":"An automated method for detecting systolic peaks from arterial blood pressure signals","authors":"Dandu Sriram Raju, M. Manikandan, Ramkumar Barathram","doi":"10.1109/TECHSYM.2014.6807911","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807911","url":null,"abstract":"In this paper, we present an automatic method for determining time-location of systolic peak in arterial blood pressure (ABP) signals. The method consists of four major steps: Gaussian derivative filtering, nonlinear peak amplification, Gaussian derivative based peak finding scheme, and peak position adjustment procedure. The method is tested and validated using the standard MIT-BIR Polysomnographic database containing a wide range of ABP signals, artifacts and high-frequency noises. Our results demonstrate that the proposed method can achieve better peak detection performance while maintaining very small detection error rates for both clean and noisy ABP signals. The method achieves an average sensitivity of 99.89% and positive predictivity of 99.59% on test ABP datasets consisting of 67,125 beats. Unlike other existing methods, our method is quite straightforward and simple in the sense that it does not use search-back algorithms with secondary thresholds.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Video error concealment using Speeded Up Robust Features and affine transformation 基于加速鲁棒特征和仿射变换的视频错误隐藏
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6807917
Aravind Ranjan, A. Midya, Jayasree Chakraborty, S. Sengupta
{"title":"Video error concealment using Speeded Up Robust Features and affine transformation","authors":"Aravind Ranjan, A. Midya, Jayasree Chakraborty, S. Sengupta","doi":"10.1109/TECHSYM.2014.6807917","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807917","url":null,"abstract":"Error concealment techniques try to mitigate the effect of channel error, using spatially and/or temporally neighboring macroblocks. This paper proposes a novel method for temporal error concealment. The change from one frame to the next frame is modelled as an affine transformation and Speeded Up Robust Features (SURF) algorithm is used to find correspondence between present and past frame. The set of matching points between the two frames is used to find an affine transformation. Random Sample and Consensus (RANSAC) algorithm is used to effectively remove outliers. The past frame is then affine transformed using the transformation matrix obtained. Corrupted regions are concealed using Temporal Replacement (TR) in the current frame with the transformed past frame as reference. Experimental results established the efficacy of the proposed algorithm over other temporal error concealment scheme in terms of both objective and subjective measurements.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121784225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A modified thinning strategy to handle junction point distortion for Bangla characters 一种改进的细化策略来处理孟加拉字的连接点失真
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6807913
Soumyadeep Ghosh, Soumen Bag
{"title":"A modified thinning strategy to handle junction point distortion for Bangla characters","authors":"Soumyadeep Ghosh, Soumen Bag","doi":"10.1109/TECHSYM.2014.6807913","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807913","url":null,"abstract":"Thinning which is an important preprocessing step for character recognition is often subject to several kinds of distortion. Junction point distortion is a major imperfection in thinned images especially for handwritten Indian scripts due to the presence of large number of complicated junctions in them. Such distortion does allow the optical character recognition (OCR) systems to exploit the properties of these junctions for character recognition. We present a novel methodology to reduce distortion at junction regions adjoining the matra for BangIa script. Our method uses geometric properties of the junctions to solve the problem. We have tested our approach on our own data set consisting of a variety of isolated handwritten character images by different writers and have got promising results.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127911585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Double-fault tolerant architecture design for digital adder 数字加法器双容错结构设计
Proceedings of the 2014 IEEE Students' Technology Symposium Pub Date : 2014-05-01 DOI: 10.1109/TECHSYM.2014.6807932
Atin Mukherjee, A. Dhar
{"title":"Double-fault tolerant architecture design for digital adder","authors":"Atin Mukherjee, A. Dhar","doi":"10.1109/TECHSYM.2014.6807932","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807932","url":null,"abstract":"In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off between area overhead and number of faults tolerated. This paper presents fault tolerant architecture design for a ripple carry adder and a conditional sum adder as fast adder assuming single and double faults. The philosophy can be generalized for any other system which has structural regularity within it.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127924820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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